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Observer
Observer
6,253 Views
Registered: ‎12-05-2008

MIG VHDL Simulation problem

I'm trying to run the testbench simulation genrated by mig2.1 using ModelSim 6.2e and I've found that if I generate verilog code then I can run the simulation fine however if I follow all the same steps but genarate VHDL code I get errors saying

 

 ** Error: (vsim-3067) Debug module 'C:/Modeltech_6.2e/xilinx_libs/unisim.fd(fd_v)' called from nondebug module 'work.tb_top(syn)'.
#         Region: /sim_tb_top/u_mem_controller/u_tb_top

 

Has anyone else managed to simulate the VHDL code succesfully?  I've not made any changes at all yet.

 

Thanks

 

Richard

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Xilinx Employee
Xilinx Employee
3,813 Views
Registered: ‎07-11-2011

Hi,

 

I am not sure if the problem is resolved.

But MIG 2.1 is very old, could you please upgrade to latest versions.

 

If not can you make sure that you have compiled libraries for both VHDL and verilog?

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Xilinx Employee
Xilinx Employee
3,799 Views
Registered: ‎03-23-2010

Did you make it in the same directory as your other design? Make sure you make a new one as I've seen some problems with that before.
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