10-03-2020 10:49 AM
I am looking into the idea of using one clock input to an Artix-7 FGPA to satisfy the clocking requirements for a MIG core. In particular I would like to use a lower frequency clock source perhaps a high quality 100Mhz for example as the input to the FPGA. Once the 100Mhz signal is in the FPGA a PLL would be used to multiply up the frequencies to the required 200Mhz for CLK_REF and 333.333Mhz for sys_clk_i.
UG586 Page 41 has a mention of the "no buffer" option for bringing clocks into a design for use in a MIG core. UG586 states "No Buffer option must only be selected for designs that already have a system input clock assigned that meets all rules specified in the Clocking, page 210".
I take this to mean that if I use the exact imputs that MIG itsself gives us for SYS_CLK_i and instead of the sys_clk_i at 333.333MHz I input the 100Mhz clock I would meet all the placement constaints for SYS_CLK_i and satisfy the requiremtns given on page 210.
I am a little concerned as to how sound this idea is and would like confirmation. This is in a large part because all the requirements on page 210 of UG586 as they relate to the location of the sys_clk_i input pins seem to be assuming that the sys_clk will be used at the frequency that it is when it is input and no additional PLL is included. It seems that the requirements of Page 210 in fact to not address the "no_buffer" case at all. Yet "no_buffer" is an allowed setting for both sys_clk_i and REF_CLK so what we are trying to do is OK by what is said in UG586. But I like to be sure. Can somebody who is really in the know comment on this?
FYI. I have implemented the otherwise exactly the same example designs with the no buffer option (PLL added for frequency shift) and the buffered option (No mods at all) and run them through timing analyzer (No failures) and timing simulations (No failures) so there is reason to think the idea is sound. Or at least Vivado is not flagging an error.
10-22-2020 08:38 PM
Seems that you are generating the sys clock and ref clock through clock wizard/pll, so you can configure IP to no buffer.
One more item here is, you can configure ref clock to "use system clock". When sys ref is 200 MHz then you can configure ref clock to "use system clock".
10-22-2020 10:37 PM
You state "Seems that you are generating the sys clock and ref clock through clock wizard/pll, so you can configure IP to no buffer." Yes, I thought I made that clear but perhaps not. Now that we agree that.this is the case we can move on to the question itself, which I am not sure I see a clear answer.
The question remains, yes no, is it safe and reliable to use this method of supplying clocks to the MIG IP? If there is only a "maybe" answer then the maybe case needs a detailed explanation of the things that must be checked to move from maybe to yes.
10-22-2020 11:13 PM
Clocking recommendations are clearly documented in user guide and should follow them.
However I believe in your request i didnt find any potentially issue. Earlier, i seen use case where customer configured sys/ref to 200MHz with No buffer, generating the sys clock and ref clock through clock wizard.
11-03-2020 09:24 AM
I wanted to put closed to this case. After checking from several sources I can clearly say that it is OK to use an external clock and using internal PLLs make the required sys_clk_ and clk_ref.
Best practice includes using a quality input clock (Exact numbers not available).
In my tests I used the CC input that MIG had identified as the location of sys_clk. to bring the first stage clock into the design. Of course you must use a CC input and the sys_clk selected input brings you to the tiles MIG is using.
As Partap states you also must configured sys/ref to 200MHz with No buffer, generating the sys clock and ref clock through clock wizard.