02-13-2019 05:28 PM
I've got the MIG to test each calibration stage in my design with my custom board on ZYNQ ultrasacle+
So, I just set the calibration stages that are skipped all first, and then, i showed the calibration skipped.
However, when i recovered the original status, calibration is failed.
DQS gate, calibration first stage in MIG, is failed.
I don't understand this situation but, i guess the PHY IOB or PHY data-line is broken by generated reverse current leakage. but .. it's just my speculation.
therefore my questions are:
- how can i make the recover my board?
- what is the reason why calibration is failed?
Thank you in advance.
02-13-2019 05:36 PM
First I would always keep all the calibration stages left at their default values as generated by the IP. If you skip calibration stages then the DDR interface will not be able to function.
It sounds like you restored the original values but you're still seeing a DQS_GATE failed status. The recommendation here is to start with the Debugging section of PG150 starting on page 580. A link is in my signature. First I would simplying everything by using the IP Example Design instead of your full application design. Next you can follow the Debugging section with the General Checks section or take a look at AR#68937 linked here:
Do the basic schematic and power rail checks to make sure the connections and termination are correct, make sure the voltage rails are at their nominal value and seem stable, then you can try running the interface at a slower rate to see if that helps. Then depending on the failing calibration stage PG150 will give you guidance on what to check next.
02-13-2019 06:18 PM
Did you have a try with MIG IP example design without any modification on this board? If it fails, please aslo test on another board to check if the problem is only found on this board.
02-13-2019 06:39 PM
02-13-2019 06:45 PM