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nasrmiad
Visitor
Visitor
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Registered: ‎08-13-2013

MIG "init_calib_complete" signal does not go high during simulation

Hi,

 

I have generated the MIG version 2.0 in Vivado, and I want to simulate the generated example design using xsim. I have implemented the design and and it works as expected on the FPGA board. But the design doesn't seem to work when I do a behavioral simulation of it.

 

I have let the behavioral simulation run 50us, but the DQ, DQS_n and DQS_p signals are in high impedance state, and init_calib_complete signal is low. I generated the MIG for MT8KTF51264HZ-1G9 DDR3 SODIMM.

 

for the MIG controller, the SIM_BYPASS_INIT_CAL parameter is set to "FAST". Is there a way to select the "SKIP" parameter instead so that the calibration sequence is skipped and our time is saved?

 

In general, for what period of time should I simulate the design so that the calibration sequence is complete? And how to reduce this time so that each time we want to run the simulation we dont have to wait so long?

 

Regards,

Miad

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vsrunga
Xilinx Employee
Xilinx Employee
7,378 Views
Registered: ‎07-11-2011

Hi,

 

Simulation period depends on how big is the memory part  but in general i guess it is not more than 30 minutes.

SIM_BYPASS_INIT_CAL = SKIP is not supported for 7 series.

I hope this is example design simulation as is.

If not, do let us know any changes that are made manually in the clock or reset path.

If you could share us the ISIM log we will have a clue what where does the simulation hang.

Also it would be good to have your mig.prj and xdc.

 

 

Regards,

Vanitha.

 

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