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sriramv90
Visitor
Visitor
8,201 Views
Registered: ‎07-30-2015

MIG read simulation works synthesis fails

Hi,

 

We are trying to run the MIG design after simulating it. We are able to read the value correctly and after synthesizing on the hardware, the value is erroneous(0xbbbbbbbb or 0xeeeeeeee) and does not change for different address. We are using Vivado 2015.2 with Zynq ZC706 board. Please advice.

 

Thanks,

Sriram.

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vsrunga
Xilinx Employee
Xilinx Employee
8,187 Views
Registered: ‎07-11-2011

@sriramv90

 

Is this example design?  Where are you changing the address?

 Are you sure you are monitoring the data after calib_done assertion, if not the controller would write and read certain patterns which you can ignore.

if this is user data please upload a wlf file that shows the behaviour.

 

 

Hope this helps

 

-Vanitha 

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