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Explorer
Explorer
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Registered: ‎02-27-2018

MIG test on VC707 single ended clock / differential clock

Hello,

 

I implemented to versions of the MIG for the VC707 one using a single end clk_sys and one using a differential clk_sys.

In both versions i tied the init_calib_complete to a led on the VC707 board and tied the sys_rst to a push button on the VC707 board.

When i implement the MIG with the differential clock (pin E19/E18) there is no problem i see the led (init_calib_complete) litten after a press on the reset.

But when i implement the MIG with the single ended clock (pin E19) i never see the init_calib_complete go to 1 (on the LED)

 

Does the MIG for the VC707 only work for a differential clock?

 

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Moderator
Moderator
491 Views
Registered: ‎11-28-2016

Hello @lebowski,

 

I can see why this might not work.

The VC707 MIG, the board, and the constraints are setup for a differential clock source for the IP.  If you configure the IP for single ended then you'll have to make sure the sys_clk option for the IP is set to single ended, you'll have to change the reference clock setting or make manual edits so this is properly driven to the MMCM, you'll probably have to change the sys_clk IO standard, and from the board level the single ended component of the clock from pin E19 may not be able to achieve the proper voltage levels to be seen as a single ended signal.  The IP itself does support a single ended clock mode but the VC707 as Xilinx delivered it was meant to be used as differential.  

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