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ahmad.zaklouta
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Registered: ‎03-07-2018

MIG write confusion in ug586

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Hi!

I am confused about the figure 1-77 in ug586.

I have a 1 GB DDR3 in KC705. After I generated the MIG core, the app_wdf_data is 512 bit (64 * 8) as the burst length is 8. my understanding of that is that I provide a write command with one address and 512 bit of data and the MIG do 8 writes to the DDR. Is this right? and then I add to the address 512 to write the next 512 bit.

from figure 1-77, the address is 28 bit so it seems like a 1GB DDR and it seems that I should provide just part of the app_wdf_data (64 bit) each clock cycle with a write command. Is this the case or what I have understood?

when it says that the MIG makes 8 write to the DDR. Does that mean eight 64bit writes or eight 8bit writes?

also is the 28 bit address for 512 bit block or for 64 bit block?

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rpr
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Registered: ‎11-09-2017

Hi @ahmad.zaklouta 

Yes your understanding is correct MIG native iinterface supports only burst length 8, so address should get incremental by 8.

Regards
Pratap

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rpr
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Registered: ‎11-09-2017

Hi @ahmad.zaklouta 

I have a 1 GB DDR3 in KC705. After I generated the MIG core, the app_wdf_data is 512 bit (64 * 8) as the burst length is 8. my understanding of that is that I provide a write command with one address and 512 bit of data and the MIG do 8 writes to the DDR. Is this right? 

-Yes your understanding is correct, one address and 512 bit of data and MIG do 8 writes to the DDR.

 

from figure 1-77, the address is 28 bit so it seems like a 1GB DDR and it seems that I should provide just part of the app_wdf_data (64 bit) each clock cycle with a write command. Is this the case or what I have understood?

when it says that the MIG makes 8 write to the DDR. Does that mean eight 64bit writes or eight 8bit writes?

also is the 28 bit address for 512 bit block or for 64 bit block?

-Memory address bus width(ADDR_WIDTH) is equal to RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH

-Data width is 64 so it is eight 64bit writes

-If Data width is 32 so then it will be eight 32bit writes

Regards
Pratap

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ahmad.zaklouta
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Registered: ‎03-07-2018

Hi @rpr 

Thanks for your answer. I think I got it now. one last thing:

In this case, to write the next 512 bit block I should increment the address by 8 not by one.

for example: this address x''0000_001'' for the second 64 bits or for the second 512 bits

And

Is it possible to use the mask for read data or it is just for write data?

 

Thanks in advance.

 

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ahmad.zaklouta
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Registered: ‎03-07-2018

Hi @rpr 

 

could you please help me with the last reply.

 

thanks in advance

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rpr
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Registered: ‎11-09-2017

Hi @ahmad.zaklouta 

Yes your understanding is correct MIG native iinterface supports only burst length 8, so address should get incremental by 8.

Regards
Pratap

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