MIG write/read error in ChipScope

[shijun]

Hi.

I have a little trouble about using the MIG to write/read the sdram chip EDE2516ABSE.I recently published a similar post:http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/Create-Custom-Part/td-p/171380.

And I so sorry not to reply it.Then I try to build a project and create a custom memory part base on EDE5116AXXX-8E .Parameter:

trcd and trp is 12.

And I use the ChipScope to monitor the signal.Here is the waveform:

you can see I write some data to the sdram after calib_done success.But the trouble is the data I read from the MCB is a little different to the data I had wrote.For example,the first data is 64'h31302f2e2d2c2b2a,but I read out 64'h31302f2c2d2c2b28!(I use to 64 bit port)

It's looks like every 1st and 5th byte data are error.

I also download the example_design,I think it can write/read correctly.

So,what's wrong with my project?or ChipScope set?

Thanks!

[shijun]

Datasheet of EDE2516:http://www.elpida.com/en/products/eol/ddr2.html

[eteam00]

Three questions:

• What FPGA device are you targeting?
• Have you seen similar results on other copies of this board?
• What data patterns have you tested?

-- Bob Elkind

[shijun]

Hi,Bob

What FPGA device are you targeting?

I use xc6slx16-3csg324

Have you seen similar results on other copies of this board?

I have seen a topic of " DDR2 Data Errors"http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/DDR2-Data-Errors/td-p/165932.

But I think my situation is different with him.

What data patterns have you tested?

I write the test data in the port c3_p0_wr_data,and read from port c3_p1_rd_data.

The port p0's timing here:

**************************timing**********************************************

c3_clk0              ＿/￣\＿/￣\＿/￣\＿/￣\＿/￣\＿/￣\＿/￣\＿/￣\＿/￣\＿......

wr_8bit_data    =><00><01.><02><03.><04><05.><06><07.><08><09>....

c3_p0_wr_en  ＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿.../￣\＿＿＿

c3_p0_wr_dataXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX<0706050403020100>

*********************************************************************************
c3_p0_wr_en    ＿＿＿/￣\＿＿/￣\＿＿/￣\＿＿/￣\＿＿＿＿＿＿＿
c3_p0_wr_data  --<=00=><=01=><=10=><=11=><=00=>---------
c3_p0_cmd_en   ＿＿＿＿＿＿＿＿＿＿＿＿＿＿/￣\＿＿＿＿＿

c3_p0_byte_addr<=====00000000===========><00000020

c3_p1_cmd_en  ＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿/￣\＿＿

*************************code*************************************

assign c3_p0_cmd_instr = 3'b000;
assign c3_p0_cmd_bl = 6'h03;
assign c3_p0_wr_mask = 0;

 always @ (posedge c3_clk0,posedge c3_rst0)
  if(c3_rst0)
   wr_current <= WR_IDLE;
  else wr_current <= wr_next;

  always @ *
   case(wr_current)
    WR_IDLE:if(wr_en)wr_next = WR_1ST;else wr_next = WR_IDLE;
    WR_1ST:if(!fifo_empty)wr_next = WR_2nd;else wr_next = WR_1ST;
    WR_2nd:if(!fifo_empty)wr_next = WR_3th;else wr_next = WR_2nd;
    WR_3th:if(!fifo_empty)wr_next = WR_4th;else wr_next = WR_3th;
    WR_4th:if(!fifo_empty)wr_next = WR_5th;else wr_next = WR_4th;
    WR_5th:if(!fifo_empty)wr_next = WR_6th;else wr_next = WR_5th;
    WR_6th:if(!fifo_empty)wr_next = WR_7th;else wr_next = WR_6th;
    WR_7th:if(!fifo_empty)wr_next = WR_8th;else wr_next = WR_7th;
    WR_8th:if(wr_en)wr_next = WR_1ST;
       else wr_next = WR_IDLE;
    default:wr_next = WR_IDLE;
   endcase

  always @ (posedge c3_clk0)
   case(wr_next)
    WR_1ST:c3_p0_wr_data[7:0] <= wr_8bit_data;
    WR_2nd:c3_p0_wr_data[15:8] <= wr_8bit_data;
    WR_3th:c3_p0_wr_data[23:16] <= wr_8bit_data;
    WR_4th:c3_p0_wr_data[31:24] <= wr_8bit_data;
    WR_5th:c3_p0_wr_data[39:32] <= wr_8bit_data;
    WR_6th:c3_p0_wr_data[47:40] <= wr_8bit_data;
    WR_7th:c3_p0_wr_data[55:48] <= wr_8bit_data;
    WR_8th:c3_p0_wr_data[63:56] <= wr_8bit_data;
    default:;
   endcase

  always @ (posedge c3_clk0)
   if(wr_next == WR_8th)
    c3_p0_wr_en <= 1'b1;
   else c3_p0_wr_en <= 1'b0;

******************************************************************

p0 address:

always @ (posedge c3_clk0,posedge c3_rst0)
 if(c3_rst0)
  wr_addr <= 30'h0;
 else if((c3_calib_done) & (c3_p0_cmd_en))
  wr_addr <= wr_addr + ADDR_INC;                     //ADDR_INC = 'h20

And p1:

assign  c3_p1_cmd_byte_addr = wr_addr - 2 * ADDR_INC;

assign c3_p0_rd_en = ~ c3_p1_rd_empty;

 assign c3_p0_cmd_instr = 3'b001;
 assign c3_p0_cmd_bl = 6'h03;

****************************************************************

So you can see I write the data to c3_p0_wr_data as:  64'h21201f1e1d1c1b1a.

But I read the data from c3_p1_rd_data is:                     64'h21201f1c1d1c1b18.

[eteam00 · Accepted solution]

Do you have more than one circuit board?

If yes, do all the circuit boards behave the same?

Have you tried a number of different data patterns, to try to correlate the error with data pattern, address pattern, etc. etc.?

What other data patterns have you tested?

-- Bob Elkind

[shijun]

Thank you very much,Bob.

Yeah,I replaced another circuit board,and I can read correct data!

[shijun]

I wonderful that the example_design write the datas as 'h00000200,'h00000208,''h00000210...

So that I use the example_design to test my old sdram which one can not work properly, it cann't find the error,because it dosen't test the lowest 3 bits(unfortunately,they are broken).

And I interested in why only the lowest 3 bits are broken?

[eteam00]

You have very clearly and dramatically demonstrated the value of building multiple copies of a new and untested board design.  This has saved you countless hours of design debugging for a problem which you have now proven to be a component or assembly fault.  Well done!

The generic answer to 'what is the cause of failure':  either component failure or assembly failure.

More often than not, the cause is assembly failure (or damage) rather than component failure.  Visually inspect the board for broken traces or solder whiskers.  Have the board cleaned.  With the board grounded on an anti-static mat, blow some air across it.  Check for missing or misaligned components (e.g. decoupling caps).  Check voltage supplies with an oscilloscope.  See if the board works properly.

If the board is still failing, and if the board is valuable to you, try replacing the DRAM on the board.  If still broken, try replacing the FPGA on the board.

-- Bob Elkind

[shijun]

Thanks,Bob.

I will follow these methods to solution the problems later.