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joe306
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Registered: ‎12-07-2018

Mapping PL into PS DDR Controller

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Hello, I would like to learn how I can map the PL AXI Master into the PS DDR Controller. Are there any examples that I could try? I have a ZCU-104 and ZCU-106 Eval Board. What documentation is there that can help me? 

 

Thank you,

Joe

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calebd
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Registered: ‎01-09-2019

@joe306 

That is actually quite difficult as I don't know what else is in the path between your PS and the PL MIG (likely an interconnect but potentially a DMA or something else).  The interconnects in the path also have the potential for a couple of cycles of delay, but that depends on the configuration.  Finally, the MIG creates a couple of cycles of delay but it depends on how you have your access pattern set up.

Some reading will help with an understanding of how these components cause various delays and will interplay with each other:

UG1085 for the PS: https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

PG150 for PL MIG: https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

PG059 for AXI Interconnect: https://www.xilinx.com/support/documentation/ip_documentation/axi_interconnect/v2_1/pg059-axi-interconnect.pdf

or PG247 for SmartConnect: https://www.xilinx.com/support/documentation/ip_documentation/smartconnect/v1_0/pg247-smartconnect.pdf

and optionally if you use a DMA, PG021 for AXI DMA: https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf

Thanks,

Caleb


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rpr
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Hi @joe306 

I believe you are looking to interface PS DDR, however logic implemented in PL. Map the PL AXI Master into the PS DDR Controller

Information is provided in UG1085 https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

Regards
Pratap

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joe306
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Hello, thank you very much for responding to my message. Quick question, how could I calculate the number of clock cycles for the PS Side to do a write in the PL-Side DDR memory?

 

Thank you,

Joe

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calebd
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Registered: ‎01-09-2019

@joe306 

That is actually quite difficult as I don't know what else is in the path between your PS and the PL MIG (likely an interconnect but potentially a DMA or something else).  The interconnects in the path also have the potential for a couple of cycles of delay, but that depends on the configuration.  Finally, the MIG creates a couple of cycles of delay but it depends on how you have your access pattern set up.

Some reading will help with an understanding of how these components cause various delays and will interplay with each other:

UG1085 for the PS: https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

PG150 for PL MIG: https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

PG059 for AXI Interconnect: https://www.xilinx.com/support/documentation/ip_documentation/axi_interconnect/v2_1/pg059-axi-interconnect.pdf

or PG247 for SmartConnect: https://www.xilinx.com/support/documentation/ip_documentation/smartconnect/v1_0/pg247-smartconnect.pdf

and optionally if you use a DMA, PG021 for AXI DMA: https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf

Thanks,

Caleb


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joe306
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Hello, thank you for responding to my post. I was looking if it is possible for the PL to write to the DDR connected to the PS? For example if I have streaming data on the PL can it stream that data into the PS DDR?

Thank you,

Joe

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calebd
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@joe306 

Sorry, I had the direction mixed up.  I would suggest the AXI DMA IP to take the Stream input and output as a Memory Mapped AXI transaction to the PS which if you correctly set up your addressing will go to PS DDR.

Thanks,

Caleb


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joe306
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Thank you very much

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joe306
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Hello, if you know of any examples, please let me know.

Thank you,
Joe

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calebd
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@joe306 

This user has created a design for AXI DMA that might be of use as a starting point: http://www.fpgadeveloper.com/2017/10/using-axi-dma-in-vivado-reloaded.html

Other than that, if you right-click on an IP there should be an example design that you can open and work with.  Alternatively, there are example designs that are integrated into Vivado that you can find on the main page when you open up Vivado, or by clicking File > New Project > Open Example Project.

Thanks,

Caleb


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joe306
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Wonderful! Thank you very, very much.

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