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Explorer
Explorer
2,883 Views
Registered: ‎07-23-2009

Micron DDR4 TwinDie MT40A1G16KNR -075E Zynq Ultrascale+ PS configuration: tFAW

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Dear forum members, I am looking for clarification about the correct configuration of the above mentioned memory chip and I cannot figure out how to configure the four activate window parameter t_FAW. 

On our board we mounted 4x MT40A1G16KNR-075:E (64 Meg x 16 bits x 16 Banks x 1 Ranks) twindie

https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr4/ddr4_16gb_x16_1cs_twindie.pdf

with a total of 8 Gigabytes memory in a fly-by topology (16bits x 4chips = 64 bits data width). 

The MT40A1G16 is a device encapsulating 2 twin Micron DDR4 dies of the type MT40A1G8 (64 Meg x 8bits x 16 Banks x 1 Ranks), the reference datasheet shall be the single die one.

https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr4/8gb_ddr4_sdram.pdf

I created a document to guide my colleagues reading the datasheet and extrapolate the Zynq ultrascale processing system DDR4 memory controller parameter, but the t_FAW parameter is depending from other two timings which cannot be set in the PS GUI: t_RRD_S and t_RRD_L.

Please find the document attached with my calculations.

The question is: do we have to set the t_FAW depending on the parameters t_RRD_S and t_RRD_L (which we do not know since not settable in the GUI and go for the minimum values of this two) or we have to set a t_FAW parameter arbitrarily big enough that the GUI sets t_RRD_S and t_RRD_L big enough to meet the datasheet requirements (which gives MIN values only?)

If somebody can give me a correct answer, I beg for references to clarify it.

This is what I found:

https://www.systemverilog.io/ddr4-initialization-and-calibration

https://www.systemverilog.io/understanding-ddr4-timing-parameters

https://www.systemverilog.io/ddr4-basics

The four activate window shall not be a problem anymore in DDR4 systems (in DDR3 I read it was a bottleneck for performances). In our case performances are not a problem, but I want to have a clear explaination about how the vivado GUI handle this parameter.

Thanks in advance

E.

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Xilinx Employee
Xilinx Employee
2,667 Views
Registered: ‎02-21-2019

Hi @emanuele83

Firstly, I reviewed your thorough documentation and have verified that your GUI settings are correct except for tfaw, which is larger than it needs to be.

Now, for your question on t_RRD, the tools automatically handle the t_RRD settings and you just need to ensure to set the tFAW. 

For your Micron part, per the datasheet for 2400 speed and 1K page size, tfaw = Min of 20CK or 21ns, so would set atleast 21ns as the tfaw.

You could throttle the peak efficiency with a larger tfaw (25ns) and save some power, assuming you’re regularly hitting the 4 Activate rolling window restriction. 

Hope this helps.

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6 Replies
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Explorer
Explorer
2,768 Views
Registered: ‎07-23-2009
Got no answer, just up for the win.
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Teacher
Teacher
2,759 Views
Registered: ‎07-09-2009
Hi Mr Pease,
your back from the dead,

We used to speak about analog things and left handed people, you have moved over to the dark side of digital design then..
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Explorer
Explorer
2,758 Views
Registered: ‎07-23-2009
eheheheh

the spirit of the good old Mr.Pease will be always with all of us. Every time an engineer messes up with analog electronic, I am sure his ghost is with him, whispering.
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Xilinx Employee
Xilinx Employee
2,668 Views
Registered: ‎02-21-2019

Hi @emanuele83

Firstly, I reviewed your thorough documentation and have verified that your GUI settings are correct except for tfaw, which is larger than it needs to be.

Now, for your question on t_RRD, the tools automatically handle the t_RRD settings and you just need to ensure to set the tFAW. 

For your Micron part, per the datasheet for 2400 speed and 1K page size, tfaw = Min of 20CK or 21ns, so would set atleast 21ns as the tfaw.

You could throttle the peak efficiency with a larger tfaw (25ns) and save some power, assuming you’re regularly hitting the 4 Activate rolling window restriction. 

Hope this helps.

------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

-------------------------------------------------------------------------

View solution in original post

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Observer
Observer
2,155 Views
Registered: ‎12-04-2018

@deepalir @emanuele83 @drjohnsmith 

Sir, We have one of the boards, where DDR4 (4Gb) chip with PS controller has been used.

The design is clamshell but we do not have Rank concept, we use single CS0 for all 4 chips [Top and Bottom] and also single ODT0.

We have tried x64 Configuration, but we are stuck at psu_init, write leveling error.

Please help us with your feedback, we are in a difficult scenario. 

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Visitor
Visitor
1,862 Views
Registered: ‎10-13-2020

About 1 month ago, our project encountered similar problem, ^_^ :

PS controller,  5 DDR4 DRAM( one for ECC purpose),clamshell pcb topology,single CS(only one bank),all of this configs lead to addressing failure.

Now we know that, 1,clamshell topology and PS controller could not be used at the same time; 2, Signal integrity simulation before hardware entity is essential.