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tdittrich
Observer
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Registered: ‎08-13-2014

Mig User Interface Back-To-Back Timing

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Hello,

 

i'm trying to implement and simulate a mig interfacing a ddr3 memory. I want to use the user interface and in view of back-to-back write commands i'm a little bit confused about its documentation in ug406.

 

Some more details about my platform:

Evalboard HTG-V6-PCIE from Hitech Global (Virtex 6 xc6vlx240-t2ff1759) with 1GB S0 Dimm Memory

ISE 14.5

Modelsim

 

In so called non-back-to-back  write command the corresponding data must not exceed a delay of 2 clock cycles. In a back-to-back command the data can exceed a delay of more than 2 clock cycles. The timing diagram (page 116, Figure 1-63, BL8) shows data presenting only with app_rdy and app_wdf_rdy static high during back-to-back transmission.

 

Questions to clarify:

(1) It is allowed that the number of data overrun the number of corresponding commands because the app_rdy is deasserted for one or more clock cycles during the back-to-back transmission?

 

(2) If (1) is not allowed does it mean i have to wait presenting data until next write commands are accepted by app_rdy='1'?

 

I expexted that app_rdy and app_wdf_rdy are interdependent. But in simulation when i try to write in back-to-back mode  to memory the number of data overruns the number of commands because app_wdf_rdy is more often high than app_rdy is.

 

Thanks in advance.

 

Kind regards

Torsten

 

 

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vsrunga
Xilinx Employee
Xilinx Employee
18,265 Views
Registered: ‎07-11-2011

Hi,

 

It is general by the time I give the command I will make sure the data is avaialbel for the controller to process.

If I satisfy the requirement for first comamnd and have continous data written as long as app_wdf_wren is high, back-to back commands will have the data ready for subsequent commands. So it would be good to make sure you do not have more than 2 clcok cycles delay for the first command so that data alignment will be proper.

 

 

Reagrds,

Vanitha

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vsrunga
Xilinx Employee
Xilinx Employee
10,799 Views
Registered: ‎07-11-2011

Hi,

 

 1) It is allowed that the number of data overrun the number of corresponding commands because the app_rdy is deasserted for one or more clock cycles during the back-to-back transmission?

--For back to back commands you can fill in data fifo as long as wdf_wren is high.

 

(2) If (1) is not allowed does it mean i have to wait presenting data until next write commands are accepted by app_rdy='1'?

--  1 is allowed, for non back to back commands make sure you follow 4:1/2:1 Mode UI Interface Write Timing Diagram in UG586

 

 

Regards,

Vanitha

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tdittrich
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Registered: ‎08-13-2014

Most of my back-to-back commands are successful in simulation. But sometimes it occures that the first data of the back-to-back command is not written to memory. Instead the data presented on app_wdf_data before app_wdf_en gone high is written to memory.

 

See picture below. Instead of the yellow marked data the blue one is written in memory. The blue one is the last data of the previous back-to-back command which was already written right. So i got the blue one twice in memory and missing the yellow one.

 

Can anybody help?

 

mig_ar.PNG

 

Best regards

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vsrunga
Xilinx Employee
Xilinx Employee
10,768 Views
Registered: ‎07-11-2011

Hi,

 

I do not see any such issues reported, I suspect if your design has any timing issues, check data alignment with respect to address, if in case the same address is latched twice you may see same data.

As this is in simulation trace down to physical interface and see what actually is happening.

 

Regards,

Vanitha

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tdittrich
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Registered: ‎08-13-2014

 

Thanks for your reply,

 

i didn't fix my problem yet. Using the back-to-back command do the first data have to be aligned with the first command? A non back-to-back command has requirements how to align the data to its command. Regarding mig documentation a back-to-back command seems to have no special requirements. In my custom design the first data have more than 2 clock cycles delay to the first command. I'm confused about how the mig can differs a non-back-to-back command  from a back-to-back command. Thanks in advance.

 

 

back_to_back.PNG

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vsrunga
Xilinx Employee
Xilinx Employee
18,266 Views
Registered: ‎07-11-2011

Hi,

 

It is general by the time I give the command I will make sure the data is avaialbel for the controller to process.

If I satisfy the requirement for first comamnd and have continous data written as long as app_wdf_wren is high, back-to back commands will have the data ready for subsequent commands. So it would be good to make sure you do not have more than 2 clcok cycles delay for the first command so that data alignment will be proper.

 

 

Reagrds,

Vanitha

---------------------------------------------------------------------------------------------
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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

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tdittrich
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Registered: ‎08-13-2014

Aligning first command with first data did the trick. Thank you very much.

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