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Visitor
Visitor
4,944 Views
Registered: ‎10-08-2008

Netlist simulation failure for DDR2 controller generated by MIG coregen

I have got DDR2 controller generated for x8, sg5E(125 MHz), BL equals to 4 using MIG. I did the synthesis and implementation using xilinx 9.2. There is one timing violation after PNR for the following constraint. 

TS_u_infrastructure_dcm_clk90 = PERIOD TIMEGRP"u_infrastructure_dcm_clk90" TS_SYS_CLK_PHASE 2 ns HIGH 50% 

 

Since I am using the ucf generated by coregen only, so I am not sure why this vioation is coming. Please throw some light on it

 

Thanks, 

Harsh Bandil

+91 9940297854 

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Xilinx Employee
Xilinx Employee
2,833 Views
Registered: ‎08-16-2007

Can you show the timing failure? Which path is failing timing? Is it a cross-clock domain path that can be ignored? If you are using a DCM, make sure that only the input clock to the DCM is constrained. If you constrain each output clock with a PERIOD constraint then cross-clock domains will be analyzed which may show timing failures on false paths.

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