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JohnsonHu
Observer
Observer
395 Views
Registered: ‎08-13-2020

Output products fail for MIG7 [IP_Flow 19-1747]

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Hi,

My original BD design uses MIG7 from VIVADO 2016.4.

This design is migrated to VIVADO 2020.1 ; however, the following message pops up and blocks the synthesis.

[IP_Flow 19-1747] Failed to deliver file 'd:/Xilinx/Vivado/2020.1/data/ip/xilinx/mig_7series_v4_2/xit/vlog_synth_rpr.xit': error renaming "d:/P20V16_4/proj_VPRD2.2B.srcs/sources_1/bd/vprd/ip/vprd_mig_7series_0_0/_tmp/vprd_mig_7series_0_0" to "d:/P20V16_4/proj_VPRD2.2B.srcs/sources_1/bd/vprd/ip/vprd_mig_7series_0_0/vprd_mig_7series_0_0": permission denied

==============================================

From AR#66991, a similar post, which states "A MIG 7 series IP core has to be configured / customized before validating or generating the output products or opening the IP example design.".

So, I re-configure MIG7, save it, and re-validate it. But the error is still.

Does the directory name "proj_VPRD2.2B" impact?

Please help.

Johnson

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kshimizu
Xilinx Employee
Xilinx Employee
287 Views
Registered: ‎03-04-2018

Hello @JohnsonHu ,

 

I don’t think it works the migration from 2016.x to 2020.x since it possibility changes the IP name/ports.   As Kren mentions, please generate a design from scrath with 2020.x. 

 

It might work from 2016.x to 2018.x, that means it upgrades two-versions.  I have not checked it, please try at your end.

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

-------------------------------------------------------

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3 Replies
JohnsonHu
Observer
Observer
343 Views
Registered: ‎08-13-2020

Hi,

(update of the previous problem)

The project name is renamed as VPRD2_2 (a shorter name and w/o '.')

However, "Create Output Product" of MIG7 is fail still with the message below ~

JohnsonHu_0-1614305046837.png

The folder under D:\P20V17_0\VPRD2_2.srcs\sources_1\bd\vprd\ip\vprd_mig_7series_0_0\_tmp\vprd_mig_7series_0_0 is valid and its contents are as below:

JohnsonHu_1-1614305644053.png

Please help to resolve this error.

 

Johnson

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kren
Moderator
Moderator
314 Views
Registered: ‎08-21-2007

Try to creat a new MIG IP into the block design and check whether the problem can be fixed.

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kshimizu
Xilinx Employee
Xilinx Employee
288 Views
Registered: ‎03-04-2018

Hello @JohnsonHu ,

 

I don’t think it works the migration from 2016.x to 2020.x since it possibility changes the IP name/ports.   As Kren mentions, please generate a design from scrath with 2020.x. 

 

It might work from 2016.x to 2018.x, that means it upgrades two-versions.  I have not checked it, please try at your end.

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

-------------------------------------------------------

Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

-------------------------------------------------------

View solution in original post