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jose09621
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Registered: ‎02-13-2019

PCB compensation due to the package delays

I found in the UG586 pg 198 from xilinx that there is information about trace length of the PCB. There it says "The package delay should be included when determining the effective trace length ". I know where to find in Vivado the package delay of the FPGA (Open implemented project -> tcl console -> write_csv flight_time.csv), but we see that those are not considerably big, e.g, the min trace delay for the bank 34 is 63.1 ps, and the max trace delay in bank 34 is 172.98, so there we have
 
delta = 172.98ps - 63.1ps = 109.79ps.
 
And as I want to work with the memory at 800MHz ~ 1250ps (considering the memory is DDR3,  it'd be 625ps) I was thinking that delta is not considerably big. would the effect of those package delays be  ignored?.  what do you think?
 
In the UG586 the relationships of  "DQ to DQS Skew Limit" , "CK to Address/Control Skew Limit" and also a CK/ DQS relationship are given. Do those relationships need to be strictly reached? , i.e, are those critical requirements over the success of the functionality? I'd say yes, because as in the UG586 for one of those relationships it says: " ensure calibration can align DQS/DQS# to the correct CK/CK# clock cycle.  Write Calibration failures are seen if this specification is violated  ". But I'd like to know your opinions about that.
 
thanks
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necare81
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Registered: ‎03-31-2016

All those values are significant.  The allowed skew for DDR3 is in the 10s of ps range according to the PCB Design guide for Ultrascale (UG583).  I am not sure which family UG586 is for but the requirements are there for good reason

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jose09621
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Registered: ‎02-13-2019

Hi @necare81 , I'm working with Kintex 7. Thank you for mention the UG583, despite it is indicated for Ultrascale I saw in the section "General Memory Routing Guidelines" some useful and clarifyng points to me that I think have no problem to use with 7-series, as:

"1- Include package delay in routing constraints when determining signal trace lengths. When minimum and maximum values are available for the package delay, use the midrange between the minimum and maximum values."

and

"3-Signal-to-signal skew constraints in this chapter are presented in the form X to Y, where the Y signal is the reference point. Within the specified constraint, signal X can be shorter or longer than signal Y. If signal X is part of a bus, then the shortest and longest signals in the bus must be within the listed specification. If the Y signal is a differential clock or signal group, then Y is defined as the mid-point between shortest and longest signals in the pair/group."

 

thanks

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kren
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Registered: ‎08-21-2007

You choose get the average delay value for each package pin. Then on the PCB layout, the skew limit is for  the total delay which include both package delay and trace length dealy.

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necare81
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Registered: ‎03-31-2016

@jose09621 UG583 has good explanations/descriptions of the routing constraints but the values should come from the documentation for the correct family, UG586 in your case.  UG586 is giving these values depending on three things, the rated speed of the memory, the rated speed of the FPGA including package and speedgrade,  and the actual usage frequency so be sure you get the right number for each constraint.

You do need to choose the correct reference signal, Y in your quote, for each type of signal you are trying to constrain.  For the DQ signals it would the average of the corresponding DQS an DQS#.  For the command and address signals it would be the average of CK and CK#.  For the DQS it would be the average of DQS and DQS# to the average of CK and CK#.

Note that DQS to CK doesn't have any adjustment for different speed ratings.

I dont see a true to complement limit in UG583 but you should be OK if you take the value for that from UG586.

 

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jose09621
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Registered: ‎02-13-2019

Thanks for the recommendation, with that I've clarified some of the doubts I had.

 

One last thing with the skew limits. I see that referent to the skew of reset_n, in Table 2-32 it is said " The signal reset_n is not required to meet the skew constraints in this table". So, is there a kind of max delay for this signal? how to know how large this trace need to be?

additionally, I noticed that in both documents UG586 and UG583, for the reset signal is recommended that  " This signal should be pulled down during memory initialization with a 4.7 kΩ resistor connected to GND ". What should be the impedance of the reset trace? (I'm using 40 ohms for the others single ended signals but the difference is that those use pull up termination).

In "Figure 2-28: Termination for reset_n in DDR3 DRAM" of the UG583 there is a representation of the reset termination, and there it is indicated a L4 impedance which in the table below Figure 2-28  (Table 2-20: DDR3 SDRAM Impedance, Length, and Spacing Guidelines for Address, Command, and Control Signals) shows a value of 39 ohms but specifies "L4 (To RTT) ". well, can I use 40 ohms of impedance for the reset trace?

thank you

 

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