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Adventurer
Adventurer
256 Views
Registered: ‎08-13-2019

how will I differentiate PL and PS ddr in the design ?

how can i access 1 GB PL DDR in the address?

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Xilinx Employee
Xilinx Employee
231 Views
Registered: ‎03-04-2018

Re: PL DDR

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Hello @veekshitha ,

 

PL DDR is included in the UltraScale architecture.  Please refer to the PG150, from page 13.

https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

 

PS DDR is included in the Zynq UltraScale+MPSoC.  Please refer to the UG1085, from page423.

https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

 

 

In order to access an external memory like DDR4 via PL DDR, firstly please create an example design PG150, page.242.  Issue the address/data/command(write, reat) at the user FPGA Logic.

 

Best regards,

kshimizu 

Product Application Engineer Xilinx Technical Support

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

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1 Reply
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Xilinx Employee
Xilinx Employee
232 Views
Registered: ‎03-04-2018

Re: PL DDR

Jump to solution

Hello @veekshitha ,

 

PL DDR is included in the UltraScale architecture.  Please refer to the PG150, from page 13.

https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

 

PS DDR is included in the Zynq UltraScale+MPSoC.  Please refer to the UG1085, from page423.

https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

 

 

In order to access an external memory like DDR4 via PL DDR, firstly please create an example design PG150, page.242.  Issue the address/data/command(write, reat) at the user FPGA Logic.

 

Best regards,

kshimizu 

Product Application Engineer Xilinx Technical Support

-------------------------------------------------------

Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

-------------------------------------------------------

MIG.PNG