[Performance benefits of using multiple DDR4 SDRAM (MIG) IPs in Zynq Ultrascale+]
Board: Zynq Ultrascale+ (ZCU106)
I am working on a high throughput real-time application that heavily relies on reading and writing the data to/from PL DDR4 memory. Currently I am using one DDR4 SDRAM (MIG) in my design to interface several AXI Master agents to the DDR4 memory. They all need to read/write to/from the same PL DDR4 memory block, sometimes at the same time.
So I am wondering is there any performance benefit to using 2 DDR4 SDRAM (MIG) in my design to improve the throughput slightly? My understanding from the Zynq U+ Technical Reference Manual is that MIG IP consist of a Physical Layer, which is basically a combination of soft cores used to configure hard DDR Memory Controller block inside the chip, and a higher-level controller layer. The following schematic from the manual on page 424 might be helpful here:
So, I would love to know if the hard block DDR Memory Controller is the ultimate bottleneck to achieving concurrent read/writes from the same PL DDR4 memory? That is, is there any performance benefit that comes from using more than one DDR4 SDRAM MIG IP to interface the same PL DDR4 memory block, if multiple read and writes are issued at the same time to the same PL DDR4 memory block?