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Adventurer
Adventurer
416 Views
Registered: ‎06-25-2018

Ping - Pong DDR3 Memory Controller with AXI4 Interface

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Hi,

I generated a DDR3 MIG IP with ping-pong enabled.  How can I have a AXI4 interface?

Regards,

Jacques

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Xilinx Employee
Xilinx Employee
346 Views
Registered: ‎08-21-2007

回复: Ping - Pong DDR3 Memory Controller with AXI4 Interface

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Only DDR3 Ping-Pong PHY is supported. Pleae design with your own controller and interface with the PHY signals.

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Xilinx Employee
Xilinx Employee
347 Views
Registered: ‎08-21-2007

回复: Ping - Pong DDR3 Memory Controller with AXI4 Interface

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Only DDR3 Ping-Pong PHY is supported. Pleae design with your own controller and interface with the PHY signals.

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