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Visitor
Visitor
7,373 Views
Registered: ‎06-25-2015

RLDRAM 3 update MIG 1.9 to MIG 2.3

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Hello,


I recently updated my RLDRAM 3 project from version MIG 1.9 build with/for ModelSim to MIG 2.3 build in and with MIG 2.3
During this update I generated a new MIG and reused my old Verilog files.
I noticed that I no longer have the ability to set the parameters for the MIG directly in the top level module mig_7series_0.
mig_7series_0 acts now as a wrapper for mig_7series_0_mig and prevents that the parameters from mig_7series_0_mig are set. Unfortunately this disables the possibility of setting the SIM_BYPASS_INIT_CAL to SKIP.
Can someone tell me why the MIG 2.3 does this and how I can stil change the SIM_BYPASS_INIT_CAL if needed ?

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Xilinx Employee
Xilinx Employee
13,670 Views
Registered: ‎07-11-2011

Hi,

 

I am unsure why you need to override it, but if in case you need so, you can edit the RTL and pass the parameter from your top level file.

Please refer below AR on how to change IP RTL

http://www.xilinx.com/support/answers/57546.html

 

 

For OOC and non OOC flow flow you can refer Vivado synthesis guide or Start a new thread in Syntheis board

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug901-vivado-synthesis.pdf

 

Hope this helps

 

-Vanitha

 

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Xilinx Employee
Xilinx Employee
7,370 Views
Registered: ‎07-11-2011

Hi,

 

MIG 2.3 unlike MIG 1.9 supports OOC, so the hierarchy has been changed to facilitate the OOC and non-OOC flows

SIM_BYPASS_INIT_CAL  is generally used to speed up simulation and can be passaed from sim_tb_top.v,  for hardware it will be set to OFF in appropraite top level files.

For any reasons you still want to change it you can set it in mig_7series_0_mig.v file

 

Hope this helps

 

-Vanitha

 

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Visitor
Visitor
7,367 Views
Registered: ‎06-25-2015

Thank you for your answer.
Currently I am doing so but it is not really a good workflow. Since I am new to Vivado may I ask if it is possible to set these parameters any other way? It seems to me like I am suppose to do so since it would match the structure perfectly if I could tell vivado to overwrite the parameters if needed. Also where can I find more information to the OOC (out of context) options in vivado ?

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Xilinx Employee
Xilinx Employee
13,671 Views
Registered: ‎07-11-2011

Hi,

 

I am unsure why you need to override it, but if in case you need so, you can edit the RTL and pass the parameter from your top level file.

Please refer below AR on how to change IP RTL

http://www.xilinx.com/support/answers/57546.html

 

 

For OOC and non OOC flow flow you can refer Vivado synthesis guide or Start a new thread in Syntheis board

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug901-vivado-synthesis.pdf

 

Hope this helps

 

-Vanitha

 

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

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