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jonas812
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Registered: ‎11-07-2010

Reset synchronization

Hello

I am using Xilinx ISE 12.2 on a Spartan 6 xc6slx150t-3fgg900 and I generated a memory interface with MIG 3.5.
The system clock (c3_sys_clk) is at 312.5 MHz and the user clocks (c3_p0_cmd_clk, c3_p0_wr_clk and
c3_p0_rd_clk) are at 50 MHz.
I didn't find any information in the datasheet, but I think that the reset (c3_sys_rst_n) should be
synchronized with the system clock to avoid the risk of it being released too closely of a clock edge, right ?
Then are the parts of the MIG working at the user clock frequency protected against this risk ?

Thanks
Jonas

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eteam00
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Registered: ‎07-21-2009

First off, you should consider updating to ISE 12.4 (and MIG 3.61).  The MIG output was updated specifically for Spartan-6 targets.  If you are unsure about this, rest easy that you can keep both 12.2 and 12.4 installed and running on the same system.

 

If you follow the reset rabbit maze through the MIG-generated files, your path will eventually lead to the file infrastructure.v (assuming Verilog).  There are quite a few reset signals in this code, and it's not easy keeping them straight.  But you do need to chase them down!

 

The default is to include a reset for the MCB_PLL.  Asserting this reset will disable the MCB_PLL outputs -- they won't toggle.  If you are using these clock outputs for your global clock -- specifically the clock for your 'synchronous reset', then you will run into a deadlock condition.  Make sure your synchronous reset isn't resetting the PLL which generates the clock for your reset.

 

In theory, the only reason for a MCB_PLL reset is to recover from SUSPEND state.  If you aren't using SUSPEND, then you should disable the MCB_PLL reset (tie it to '0', for example).  This is most easily done by manually editing the infrastructure.v file.

 

If you look through infrastructure.v, you'll find that a synchronous reset is generated in the file.  The cx_sys_rst input at the 'top layer' of the MIG design is synchronously stretched in infrastructure.v, and the stretched output is signal cx_rst_0.

 

Hope this helps.

 

-- Bob Elkind

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fmueller-co
Xilinx Employee
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Registered: ‎09-27-2010

Hi Jonas,

the reset to the MCB is synchronized inside the MCB to the sys_clk_2x domain.  There is no need to synchronize the c3_sys_rst_n signal externally.

 

And I agree with Bob that you should use the latest version of ISE as there have been several changes to the MIG core since 12.2.

 

- Frank

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eteam00
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Registered: ‎07-21-2009

the reset to the MCB is synchronized inside the MCB to the sys_clk_2x domain.  There is no need to synchronize the c3_sys_rst_n signal externally.

I'll be more direct on this question:

If you synchronise the reset signal driving the  c3_sys_rst_n input to the uncustomised MIG design -- using a clock generated from within the MIG design -- the result WILL be an unrecoverable lockup condition.

c3_sys_rst_n is connected to the PLL .RST input.  When this reset is asserted, the clock outputs of the PLL are stopped.  The stopped clocks are useless for de-asserting the c3_sys_rst_n signal, resulting in a system lockup.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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fmueller-co
Xilinx Employee
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Registered: ‎09-27-2010

Hi Bob,

you point out an important fact.  You cannot use the same PLL that you are resetting synchronously to clock your reset synchronization register.  I was simply pointing out that there is no need to synchronize the c3_sys_rst_n because we take care of this in the MIG design including the MCB. 

 

- Frank 

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jonas812
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Registered: ‎11-07-2010

Hello,

Thanks for all your answers and sorry for the delay of my answer.

As you suggested, I upgraded ISE from 12.2 to 12.4, but I didn't regenerate the memory interface with the new MIG because I didn't have a lot of time at that time and I didn't want to change something working while I have others things that doesn't work very well. The project I was working on is now officially finished.
I noticed one more thing : the c3_calib_done signal seems to need to be synchronized with the user clock (12.5 MHz in my case). I have made an auto-test of the DDR that starts right after the calib_done signal becames high and this auto-test mostly fails if the calib_done signal is not synchronized.
By the way, I am not using the clock output (clk0) nor the reset output (rst0).

Greetings
Jonas