01-02-2019 03:39 AM
We are using VU9P FPGA to interface with 9x 8-bit twin-die DDR4 devices and are running at 1066MHz. We are using default Example design and are seeing few data errors.
During SI simulations, we see that eye opening is better for OUT/IN 60 IO models (at FPGA side) and 40 ODT at DDR side as compared to OUT/IN 40 IO models. Can you please suggest us on how can we change this value in the example design?
01-02-2019 09:51 AM
The IP automatically generates the optimized values based on the FPGA, memory configuration, and memory topology based on the guidelines described in Chapter 2 PCB Guidelines for Memory Interfaces in UG583. A link is in my signature. These settings are the tested and characterized values supported by the IP. Changing the IP generated defaults is an unsupported configuration from Xilinx's standpoint since these are not guaranteed to operate across PVT for that configuration. With that said you can change the FPGA driver settings in the I/O Ports tab with a synthesized or implemented design or you can manually change them in the XDC. For the DDR4 ODT settings you'll have to manually change the Mode Register settings that are specified in the ddr4_0_ddr4.sv file in this path (simple design) /project/project.srcs/sources_1/ip/ddr4_0/rtl/ip_top/ddr4_0_ddr4.sv. You'll need to review the JEDEC or memory device spec to know which mode registers and bits you want to change. Also you'll need to edit the file outside of Vivado. If you regenerate the IP then the changes will be overwritten. Overall I would only take approach for debug purposes and would review your board layout against the rules in UG583.