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beni.falk
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Registered: ‎01-05-2020

Should we use one or two DDR controllers on (RFSoC) PL side?

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We are designing an RFSoC-based system. The system needs to incorporate DDR (on PL side).

According to my understanding we can either use a single DDR controller with 64-bit data width or two controllers with 32-bit data width each.

Our PL application comprises multiple (more than 2) processing subsystems that need to access the DDR "in parallel". All accesses will be multiples of aligned 64-byte chunks.

Assuming the same DDR clock rate in both cases, is there any advantage to using two DDR controllers as opposed to one?

Note: the ZCU216 EVB uses two DDR controllers. Does anybody know why? 

Thanks,

 

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calebd
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Registered: ‎01-09-2019

@beni.falk 

I want to confirm that you are not using the PS DDR controller for anything else?  If you are not using it, that would be a resource I would suggest looking into since it is provided within the Zynq portion of the RFSoC.

To your performance question, this is highly dependent on your traffic pattern and what you need to be sending to DDR.  You could have better performance either way depending on the exact needs of your system.  There is a multitude of factors that can go into a system-level analysis like this depending on what your exact requirements are, and how your system is architected.  I would probably suggest simulating the traffic pattern you are desiring in both a 1 controller example design and 2 controller case if you need to see an A/B comparison.

I would also suggest looking at our guidance for performance per PG150 on page 19: https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

In addition, you will want to consider how our controller handles AXI traffic addressing.  This post should help with that question: https://forums.xilinx.com/t5/Memory-Interfaces-and-NoC/How-to-map-the-AXI4-address-to-the-ddr4-memory-address/td-p/954407

Thanks,

Caleb


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beni.falk
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Registered: ‎01-05-2020
I forgot to mention that we need maximum possible overall DDR data throughput
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calebd
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Moderator
490 Views
Registered: ‎01-09-2019

@beni.falk 

I want to confirm that you are not using the PS DDR controller for anything else?  If you are not using it, that would be a resource I would suggest looking into since it is provided within the Zynq portion of the RFSoC.

To your performance question, this is highly dependent on your traffic pattern and what you need to be sending to DDR.  You could have better performance either way depending on the exact needs of your system.  There is a multitude of factors that can go into a system-level analysis like this depending on what your exact requirements are, and how your system is architected.  I would probably suggest simulating the traffic pattern you are desiring in both a 1 controller example design and 2 controller case if you need to see an A/B comparison.

I would also suggest looking at our guidance for performance per PG150 on page 19: https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

In addition, you will want to consider how our controller handles AXI traffic addressing.  This post should help with that question: https://forums.xilinx.com/t5/Memory-Interfaces-and-NoC/How-to-map-the-AXI4-address-to-the-ddr4-memory-address/td-p/954407

Thanks,

Caleb


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our
Versal Blogs

------------------------------------------------------------------------------------------------

View solution in original post

beni.falk
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Registered: ‎01-05-2020

Thanks!

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