Simulating MIG DDR3 example testbench in Modelsim DE

[electricfox]

Hello,

I generated a model for the 1Gb Micron DDR3 module included with the SP-605 evaluation kit.  I used version 3.2 of the MIG tool to generate the module in vhdl and am trying to simulate the example testbench in Modelsim DE 6.5c (mixed language) using the sim.do script also generated by MIG.

With DE being a new release of Modelsim, there were a number of missing library modules which had to be re-compiled from the command line.  The script is running - but with one major error, which prevents sucessful simulation:

 # ** Warning: (vsim-3473) Component instance "samc_0 : mcb" is not bound.
#    Time: 0 ps  Iteration: 0  Region: /sim_tb_top/design_top/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst  File: ../rtl/mcb_raw_wrapper.vhd

It appears that the script cannot find the module called mcb in any of the libraries.  In the directory, $XILINX/secureip/mti/mcb_mti, there resides encrypted verilog ip for V_MCB and MCB_WRAP modules.

Does anyone know how to compile the mcb module into the relevant library (I think it might need to go in unisims or secureip, but am not sure which...)?

Many thanks indeed for any assistance you can provide!

[electricfox · Accepted solution]

Thanks to anyone who looked over this problem.  I've now managed to solve it and thought I'd share the solution with the forums for posterity.

 It turns out you can compile the libraries using a Modelsim PE or SE installation.These are free to download for evaluation if you only have the DE license (you just need an SE/PE installation, not a full license).  I added the SE executable location to the path in the terminal and created a new library called "work" in my home directory.  I then ran the following command:

 /opt/Xilinx/11.1/ISE/bin/lin/compxlib -w -s mti_se -arch all -lib all -l all -dir /home/pete/new_libraries

where /opt/Xilinx/11.1/ISE/bin/lin/compxlib is the location of the compxlib executable binary and /home/pete/new_libraries is the directory I wanted to compile the new libraries into.  The -arch -lib -l all instructs this to compile all libraries for all architectures in all languages.  The final library composition came to just shy of 700 MB and took 20 odd minutes to compile.This new compilation contained the MCB module in both the Verilog and VHDL libraries.  The simulation is now running ok.  The only downside to this is that I can't think why my first compilation of the libraries omitted the MCB library, so I still don't know what caused this problem in the first place.

If I come across any further problems with my DDR3 exploits, I'll be sure to post here again.

Cheers!

[oceanlogic]

To elaborate on the answer above, the MCB component is actually in the unisim library. If you encountered the same message as I did, and was wonderring what the cause of the error was even though the secureip library was compiled, make sure unisim library is correctly compiled and mapped.