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dimitris78
Adventurer
Adventurer
1,459 Views
Registered: ‎09-13-2019

Simulation not working in DDR example design

I create the example design for a ddr3 interface in a folder in my home directory (windows 10, vivado 2019.1). The example design opens up and when I click "Run simulation" I get the following error message popup from vivado:

Unable to open file '' because file does not have read permission. Would you like to open the directory instead?

Every other example design for other IPs I opened up I could simulate fine.

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8 Replies
kren
Moderator
Moderator
1,423 Views
Registered: ‎08-21-2007

Are you running simulation within Vivado or third-party simulator?

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dimitris78
Adventurer
Adventurer
1,416 Views
Registered: ‎09-13-2019

Running it in Vivado.

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1,274 Views
Registered: ‎12-18-2019

I have a problem similar to dimitris78.

I was able to simulate the block memory when instantiated in a module lower in the hierarchy, but when I instantiate that lower module into another module and try to simulate it I get the following message:

"Unable to open file 'blk_mem_gen_v8_4.v' because file does not have read permission. Would you like to open the directory instead?"

When I choose to open the directory, it won't because: "A background task is running. Please wait until it completes and try again."  The background task never completes (it's waiting for the first message to be cleared.)  I've tracked down all instances of blk_mem_gen_v8_4.v and changed the permissions to "Full Control", which didn't help.

Any clues would be appreciated.

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tomturbo
Observer
Observer
1,089 Views
Registered: ‎02-06-2014

I have the very same problem when simulating my own design. I am using Vivado 2019.1 and Windows 10.

I recently converted from Vivado 2017.4 The problem was not present there.

When I hit "OK" the next message is "A background task is running. Please wait until in completes and try again.". When I hit OK, the frist message appears again and so forth and so forth.I cannot do anything because I am constantly stuck in this messages.

I guess I am not the only person having this problem. When I type  "Vivado unable to" in Google then it autocompletes the whole question.  "Vivado unable to open file because file does not have read permission"

 

 

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kshimizu
Xilinx Employee
Xilinx Employee
1,057 Views
Registered: ‎03-04-2018

Hello @dimitris78 ,

 

Could you please tell us which device are you using?  I would like to try to reproduce what you mention.

-FPGA device

-Vivado2019.1, Win 10

-Vivado simulation, not 3rd-party simulation.

-DDR3

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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tomturbo
Observer
Observer
1,047 Views
Registered: ‎02-06-2014


@tomturbo wrote:

I have the very same problem when simulating my own design. I am using Vivado 2019.1 and Windows 10.

 


I am not sure if I have got the very same problem. But for me it disappears when I put a breakpoint at $finish(). Now I can simulate quite happily.

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kren
Moderator
Moderator
1,037 Views
Registered: ‎08-21-2007

 Is it the design of Ultrascale/Ultrascale+? For DDR3 simulation, set the xsim.simulate.xsim.more_options to -testplusarg model_data+./. The Generate Scripts Only option generates simulation scripts only. To run behavioral simulation, Generate Scripts Only option must be de-selected.

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eanema
Visitor
Visitor
46 Views
Registered: ‎01-23-2019

I have the same situation as tomturbo, although I'm using Vivado 2019.2:

When I hit "OK" the next message is "A background task is running. Please wait until in completes and try again.". When I hit OK, the frist message appears again and so forth and so forth.I cannot do anything because I am constantly stuck in this messages.

In my case I eventually figured out (no thanks to the Vivado simulator's amazing error messages...) it was because I was attempting to access element zero of an array declared as:

type byteArray is array(positive range <>) of std_logic_vector(7 downto 0);

instead of with natural range <>. So clearly that is an error, but it was not clear what the problem was. 

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