Slow Calibration in 7-series DDR3 Simulation

[jeffchen]

Hi all,

I have searched some related topics about this issue (https://forums.xilinx.com/t5/Memory-Interfaces/7-series-DDR3-MIG-simulation-how-to-speed-up/td-p/513715). However, I am still wondering if there is an update about this or anything helpful. Following is the description.

I am using VC707 to develop the project, the system needs to load the data from PC to the FPGA. The amount of data is huge that the DDR3 must be used. However, as the title, the simulation includes the slow calibration, it takes around 10 mins on my computer to finish the calibration. Thus, I am wondering if there is a solution about this issue now? If not, is there any suggested strategies to design with the 7-series MIG? The way I know is ether waiting for the simulation or directly load on FPGA to test. Both of them are time comsuming. Hence, any command would be extremely appreciated !   

[kren · Accepted solution]

Simulation is slow because we have to simulate the RTL for the Phaser in 7 Series. There are a variety of delays and edge adjustments in the Phaser that must be done and if one skips them then the memory system simply wont work. As you've set SIM_BYPASS_INIT_CAL = "FAST", there's no other way to get calibartion simulation faster.

[jeffchen]

@krenReally thanks for your help! It seems that we can not do anything to the provided simulation environment. I think I may develop a simple behavior model to facilitate the design.