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Visitor laurenho
Visitor
4,917 Views
Registered: ‎06-29-2010

Spartan-6 MIG Clocks

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I'm having trouble connecting clocks to the MIG I generated using Coregen. I have one clock signal coming into the FPGA (call it USER_CLK), and I want it to drive the two cX_sys_clk s of the two MCBs in the MIG. I also want the same clock to drive the user logic (read, write, command), which I have no problems (so far) doing after passing USER_CLK through an IBUFG and BUFG. However, I get this error in the Translate step when I connect USER_CLK to cX_sys_clk:

 

NgdBuild:462 - input pad net 'USER_CLK' drives multiple buffers:
  pin I on block CLK_WIZ/clkin1_buf with type IBUFG,
  pin I on block mig/memc1_infrastructure_inst/se_input_clk.u_ibufg_sys_clk with type IBUFG,
  pin I on block mig/memc3_infrastructure_inst/se_input_clk.u_ibufg_sys_clk with type IBUFG

 

I can remove the CLK_WIZ (Clock Wizard), but I'm concerned as to why I would need to remove the IBUFGs that were in the core generated by Coregen... Are there any other ways to drive the two cX_sys_clk without stripping the wrappers?

 

Thanks in advance.

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Visitor laurenho
Visitor
5,718 Views
Registered: ‎06-29-2010

Re: Spartan-6 MIG Clocks

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I merged the two infrastructure modules together and left the two wrapper modules alone. In the merged infrastructure module, I just have one PLL that drives two BUFPLL_MCBs since the MCBs are on different sides of the device. This solution is able to be synthesized and implemented.

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Xilinx Employee
Xilinx Employee
4,875 Views
Registered: ‎08-16-2007

Re: Spartan-6 MIG Clocks

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You'll have to go into the MIG generated RTL, specifically infrastructure.v/vhd and remove the IBUFG instantiations.

This also means that if you are using the MIG core in your ISE project by simply adding the .XCO you'll have to add all the RTL instead.

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Visitor laurenho
Visitor
5,719 Views
Registered: ‎06-29-2010

Re: Spartan-6 MIG Clocks

Jump to solution

I merged the two infrastructure modules together and left the two wrapper modules alone. In the merged infrastructure module, I just have one PLL that drives two BUFPLL_MCBs since the MCBs are on different sides of the device. This solution is able to be synthesized and implemented.

View solution in original post

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