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codingvhdl
Observer
Observer
9,197 Views
Registered: ‎06-25-2014

Spartan 6, PLL -> MCB 'Buffer in Series' problem

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My first time posting here, I've read the rules and I've tried searching for a similar a problem already. The closest thing I found was this, but it didn't fully help me.

 

I'm trying to just get the MCB up and running with a basic one bidirectionnal 32-bit port. I've used the MIG to create the desired component, but after connecting the required PLL as described in P.38 of UG388, I get:

 

ERROR:NgdBuild:770 - IBUFGDS
'DDR2Controller/memc3_infrastructure_inst/diff_input_clk.u_ibufg_sys_clk' and
BUFG 'PLL_4_MCB/clkout3_buf' on net 'CLKFB_OUT' are lined up in series.
Buffers of the same direction cannot be placed in series.

 

I used the Clockin Wizard to generate the PLL outputiing CLK_OUT1 (sys_clk_p) & CLK_OUT2 (sys_clk_n) with no output Buffer and CLK_OUT3 to with a buffer. CLKFB_OUT is only looped back to connect to CLKFB_IN of that same PLL.

 

- The input clock to the PLL is the 100MHZ board clock. And the three output clocks are all 100 MHz and in phase.

- The DDR2 memory is operating at 200MHz

 

 


Also, I was previously getting the below error, but today after some fiddling, it has switched to the above mentioned one. I was getting this error despite having no ouput buffers placed on CLK_OUT1 and CLK_OUT2. There was any actual design change to get the above new error, just trying new things and reverting back to the intial setup.

ERROR:NgdBuild:770 - IBUFGDS
'DDR2Controller/memc3_infrastructure_inst/diff_input_clk.u_ibufg_sys_clk' and
IBUFGDS
'DDR2Controller/memc3_infrastructure_inst/diff_input_clk.u_ibufg_sys_clk' on
net 'sys_clk_n' are lined up in series. Buffers of the same direction cannot
be placed in series.

 

 

 

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vsrunga
Xilinx Employee
Xilinx Employee
15,285 Views
Registered: ‎07-11-2011

Hi,

 

Is this in example design or user deisgn?

MIG by default gnerates required clocks, you can find PLL and BUFPLL_MCB modules in example_design(or user_design)/RTL/Clocking/infrastructure.v(.vhd) folder.

You only need to specify sys_clk pinouts.

Any reason that you again use PLL to generate the clocks?

Do you have specific cloking requirements and hence you want to go for PLL cascade ?

 

I would suggest you to follow flow -1 of this AR, synthesize the design and check sys_clk routing.

If you still see the error please upload your test project for investigation

 

 

Hope this helps

 

Regards,

Vanitha

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4 Replies
vsrunga
Xilinx Employee
Xilinx Employee
15,286 Views
Registered: ‎07-11-2011

Hi,

 

Is this in example design or user deisgn?

MIG by default gnerates required clocks, you can find PLL and BUFPLL_MCB modules in example_design(or user_design)/RTL/Clocking/infrastructure.v(.vhd) folder.

You only need to specify sys_clk pinouts.

Any reason that you again use PLL to generate the clocks?

Do you have specific cloking requirements and hence you want to go for PLL cascade ?

 

I would suggest you to follow flow -1 of this AR, synthesize the design and check sys_clk routing.

If you still see the error please upload your test project for investigation

 

 

Hope this helps

 

Regards,

Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

codingvhdl
Observer
Observer
9,126 Views
Registered: ‎06-25-2014
Sure, will do.
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dwyskiel
Visitor
Visitor
8,523 Views
Registered: ‎10-01-2013

Hi, I have a similar problem.  I am using a microblaze processor and am generating clocks using a clock generator module in the *.xmp file, instead of external clock inputs.   UG416 indicates that this should be possible.  I am using ISE 13.2 due to some additional IP that breaks when using later versions of the tool.

 

The module is called DDR3_Interface.xxx

 

Please note:  neither UG388 nor UG416 address this issue.

 

When I implement the design (using Export to SDK) I get the error message:

 

ERROR:NgdBuild:455 - logical net 'sysclk_2X_MCB1' has multiple driver(s):
ERROR:NgdBuild:455 - logical net 'sysclk_2X_180_MCB1' has multiple driver(s):

 

The console reports:

 

ERROR:NgdBuild:455 - logical net 'sysclk_2X_MCB1' has multiple driver(s):
     pin PAD on block sysclk_2X_MCB1 with type PAD,
     pin CLKOUT0 on block
   microblaze/clock_generator_2/clock_generator_2/PLL1_INST/Using_PLL_ADV.PLL_AD
   V_inst with type PLL_ADV
ERROR:NgdBuild:455 - logical net 'sysclk_2X_180_MCB1' has multiple driver(s):
     pin PAD on block sysclk_2X_180_MCB1 with type PAD,
     pin CLKOUT1 on block
   microblaze/clock_generator_2/clock_generator_2/PLL1_INST/Using_PLL_ADV.PLL_AD
   V_inst with type PLL_ADV

 

However, I have modified the DDR3_Interface.v so that the "Infrasctructure.v" component does not source the differential clocks to the DDR3_Interface and removed the NET settings from the UCF file.  ISE still insists that there is a conflict (multiple drivers) due to a connection to a pad.

 

Any help would be greatly appreciated.

 

Best,

 

David.

 

 

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wvancura
Visitor
Visitor
8,330 Views
Registered: ‎07-10-2008

If you are driving c3_sys_clk from an internal clock or one that has already been buffered with an "IBUFG",  you will need to change the input clock buffer in the infrastructure module from "IBUFG" to a "BUFG". The IBUFG demands that the clock come from a PAD not internally, which is why you get Buffer in Series or net has two sources error.  Search the infrastructure module for IBUFG or IBUFGDS depending on your using a single or differential clock.

Good luck,

Pixeltamer

 

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