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Visitor
Visitor
3,553 Views
Registered: ‎09-17-2008

Spartan6 DDR3 simulation

I'm working on a Spartan6 DDR3 design, and can't get the calibration to complete.  The example design works for me as advertised, but not my user design.  UG416, page#64 talks about some signals available for simulation, like cal_state, but for the life of me I can't find them anywhere in the design hierarchy.  I must be missing something obvious.... any hints as to where I might find these helpful but elusive signals?

 

I'm running 12.4 ise and using isim.

 

thanks.... bill

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Advisor
Advisor
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Registered: ‎10-05-2010

Are you connecting the MCB to a model of your memory chip in your test bench? The DDR2 part I've used generated a ipcore_dir/corename/user_design/sim/functional/ddr2_model_c3.v file. Have a poke around in that part of your example design to see which one you should be using.

 

If you're already doing this, perhaps you could give some more details about your test bench?

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Visitor
Visitor
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Registered: ‎09-17-2008

My test bench has my top level design and the ddr3 model that comes from Micron.  My top wrapper had several modules, and the 2 modules generated by MIG.  This looks almost exactly like the /example_design structure.

 

TOP_TB.v

 

   ddr3_model_c4.v

 

   top_wrapper.vhd

        memc4_wrapper.vhd

        memc4_infrastructure.vhd

        everything_else.vhd

 

 

My puzzle right now is where are those signals the UG refers to?  UG416 page#64 refers to some simulation only signals such as cal_state[144:0] that are part of the unisim model.  Where do I see the unisim model in ISIM?

 

Thanks.... bill

 

 

 

 

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Advisor
Advisor
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Registered: ‎10-05-2010

I really have no idea, either! I haven't needed the debug signals when simulating the MIG, though.

 

Can you perhaps post your top_tb.v for us to inspect?

 

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