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Observer
Observer
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Registered: ‎08-31-2019

Spartan6 SDRAM interface

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Hi there ,

 

I am trying to interface a 133Mhz SDRAM part number : IS42S86400F-7TLI with Spartant 6 part number : XC6SLX150T-3FGG676I , but i am not able to run tests at 133Mhz sucessfully . At this speed i dont see any data being read out at all .

Initially the output pins for the SDRAM from FPGA i.e RAS , CAS , CLOCK , WE , CS and Data lines were set at LVCMOS in the UCF with not drive strenght or slew defined .  Also there are 22ohm series resistors on the all of the these control and data lines , only pullups on Address lines .

 

I changed the the UCF so that all the control signals and Data lines are now on LVTTL with drive strenght = 16 and Slew rate to = SLOW , testing @40Mhz shows no positive results .  After changing the drive strenght to 24 i was able to read back the data sucessfully @40Mhz, but i noticed the current consumption of the FPGA increased from 1.6 amps ( with drive strenght = 16) to 1.8 amps ( drive strenght = 24).

Current UCF :


NET "SD_WE" IOSTANDARD = LVTTL;
NET "SD_RAS" IOSTANDARD = LVTTL;
NET "SD_DQM1" IOSTANDARD = LVTTL;
NET "SD_DQM" IOSTANDARD = LVTTL;
NET "SD_CAS" IOSTANDARD = LVTTL;
NET "SD_CLK" IOSTANDARD = LVTTL;
NET "SD_CS" IOSTANDARD = LVTTL;

NET "SD_CAS" PULLUP;
NET "SD_CLK" PULLUP;
NET "SD_CS" PULLUP;
NET "SD_DQM" PULLUP;
NET "SD_DQM1" PULLUP;
NET "SD_RAS" PULLUP;
NET "SD_WE" PULLUP;


NET "SD_CLK" DRIVE = 24;
NET "SD_CLK" SLEW = SLOW;
NET "SD_CS" DRIVE = 24;
NET "SD_CS" SLEW = SLOW;
NET "SD_DQM" DRIVE = 24;
NET "SD_DQM" SLEW = SLOW;
NET "SD_RAS" DRIVE = 24;
NET "SD_RAS" SLEW = SLOW;
NET "SD_DQM1" DRIVE = 24;
NET "SD_DQM1" SLEW = SLOW;
NET "SD_WE" DRIVE = 24;
NET "SD_WE" SLEW = SLOW;
NET "CK_EN" DRIVE = 24;
NET "CK_EN" SLEW = SLOW;

 

See attached screen shots at drive strenght = 16 . The signal on top is 40Mhz Clock , where as bottom signal in CAS .

Next set of images for drive strength = 24 @ 40Mhz 

DS_16.jpg
DS_16cs.jpg
DS_16scope.jpg
DS_16scope1.jpg
DS_16scope2.jpg
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Moderator
Moderator
299 Views
Registered: ‎11-09-2017

Hi @aaghouri_2019 

Did you run IBIS model ? seems that high speed board layout guidelines are not followed. Please follow the layout guidelines documenetd in spartan 6 memory user guide.

With default drive stength, at memory interface unable to detect the signal, as you increase the drive strength memory component responded but increase in drive strength made more current consumption.

Regards
Pratap

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Observer
Observer
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Registered: ‎08-31-2019
Can someone from Xilinx guide me why my FPGA which running only a simple SDRAM read and write is drawing so much current ??? and why i can only run it with drive strength = 24 ???
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Moderator
Moderator
300 Views
Registered: ‎11-09-2017

Hi @aaghouri_2019 

Did you run IBIS model ? seems that high speed board layout guidelines are not followed. Please follow the layout guidelines documenetd in spartan 6 memory user guide.

With default drive stength, at memory interface unable to detect the signal, as you increase the drive strength memory component responded but increase in drive strength made more current consumption.

Regards
Pratap

Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.

View solution in original post

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Observer
Observer
286 Views
Registered: ‎08-31-2019

Hi ,

no IBIS model was not simulated , any work around this issue like if i change series resistors from 22ohm to 30ohm or less and test the interface with less drive strength ?

I also noticed the track lenght of CAS . RAS , CS , CLK and WE are 4 inches and more on the PCB board , where as UG388 says the track lenght should be 3 inches or less .

In that case i have to replace 22ohm with less value like 5ohm in series ?

 

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275 Views
Registered: ‎06-21-2017

Those traces are not pretty.  There is a lot of signal coupling.  Did you follow all of the decoupling recommendations for the FPGA and RAM?  How many ground and solid power planes do you have?  You should have one plane between each signal layer of you can.  Are your traces impedance controlled?  Are they spaced far enough apart to mitigate cross talk?

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