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Observer
Observer
6,931 Views
Registered: ‎12-20-2011

Sub-Optimal placement for CCIO and MMCM Pair

Hi Guys,

 

Im am trying to use the VC709 and both DDR banks, but I get this error that says:

 

[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING.

 

Any ideas? Im totaly stumped on this one!

 

PS. for a more detailed error see attachment.

 

Thank you!

MIG Errors.png
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Xilinx Employee
Xilinx Employee
6,918 Views
Registered: ‎02-06-2013

Hi

 

As you are using VC709 follow the below doc and check if your pin constraint are correct.

 

http://www.xilinx.com/support/documentation/boards_and_kits/vc709/2014_4/xtp235-vc709-mig-c-2014-4.pdf

 

You can also download the design files from below link

 

http://www.xilinx.com/products/boards-and-kits/dk-v7-vc709-g.html#documentation

Regards,

Satish

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