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Explorer
Explorer
299 Views
Registered: ‎04-06-2017

The system clk input for DDR3 MIG.

I use kintex-7 410T FPGA, which has 7 HR banks and 3 HP banks. I create.a MIG IP instance with 8 DDR3 controllers. each controller reads and writes one ddr3 connected with one bank. The bank 14 and bank 15 is not for DDR3 operation. The other bank each is connected with one ddr3. The DDR3 has 16 bits data width. I do not have one pin spared for system clk input. So I set the system clk input as NO BUFFER in MIG wizard. I use a pair of clock capable differential pin in bank 14 as system clk input and set this clk as the system input clk for each controller in the MIG. I think this break the rule that the system clk should.be assaigned at the same bank as DDR3 or the adjcent bank.

Will the differential clock be automatically recognized as a global clock and buffered by BUFG and.therefore does not create large jitters leading to unexpected results?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-21-2007

回复: The system clk input for DDR3 MIG.

The tool will report an error on your clock input even throughout a BUFG. The DDR3 interface functionality cannot be guaranteed with this clocking scheme.

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Explorer
Explorer
211 Views
Registered: ‎04-06-2017

回复: The system clk input for DDR3 MIG.

I generate a bit file with a MIG IP with 3 controller controlling 3 DDR3 with 3 HP banks. one bank for one ddr3. no error is reported. I am wondering although no error is reported, the desgn may not be good.

I also generated a mig IP with 5 controller controlling 5 DDR3 with 5 HR banks. one bank for one ddr3. no error is reported. 

But error will be reported if I create  a mig IP with 8 controller controlling  8 DDR3 with 5 HR banks and 3 HP bank. one bank for one ddr3.

Can I upload my projects that successfully generating bit file to you and hope you can evaluate my design to see if it will cause problem. Thank you. one file is 70M+, another is 90M+. How can I send these large file to you?

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Explorer
Explorer
177 Views
Registered: ‎04-06-2017

回复: The system clk input for DDR3 MIG.

Thank you. The tools does not report error because my MIG has multiple controller and I choose the no buffer for the system clk. But this is not recommended according to the user MIG guide.
Now I plan to use independent system clock for each controller. The location of each system clock is the CCIO pin in the same bank as the ddr3 interface. I do not want to use many oscillators to create the clocks. Can I use multiple channels drivers such as SN74HLVC16T245 to buffer the clock? One oscillator connects the inputs of several channels of SN74HLVC16T245 and the corresponding output pins connect to each system clk pins of the MIG controller. I think there may be a problem. If the jitter can be introduced by BUFG in FPGA, will it also be introduced by buffer?
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-21-2007

回复: The system clk input for DDR3 MIG.

As the system clock input of the MIG IP will go into MMCM, so please check the intput jitter is within the MMCM spec according to 7 Series datasheet.

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Explorer
Explorer
133 Views
Registered: ‎04-06-2017

回复: The system clk input for DDR3 MIG.

What is the meaning of jitter? Is it the variation of frequency of clock signal?

The following is my understanding on jitter. It may not be correct. I hope you can give your comment which leads me to a better understanding. Thank you.

If I insert buffer external to the FPGA. I don't think it will change the freqency of the input clock. If the jitter of the original clock is within the specs of MMCM, then the jitter of output of the buffer and the input of the FPGA is also within the jitter specs..The same is also apply to the BUFG of the FPGA. Insertion of BUFG and long route will not cause large jitter.

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