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Adventurer
Adventurer
7,407 Views
Registered: ‎03-02-2015

To work around the clock cycle delay by fsm to prevent timing issue

Hi,

I have an input to my module,'ready' signal(app_rdy_1) which goes low at random time for some short duration & then goes back high.
When the ready signal goes low,i need to maintain the values of some of my signals.

I will explain for 1 signal.
1 of i/p to my module = count1(26 downto 0)
1 of o/p of my module = ui_c0_app_addr(26 downto 0)

The i/p to my module,count1 is coming from a counter.I stop the counter from incrementing when ready goes low.So obviously,the i/p to my module also stops incrementing when ready goes low.This can be seen in attached waveform.

In my module,through a fsm,i assign the count1 i/p to my o/p ui_c0_app_addr.So this gets delayed by 1 clock cycle.So when ready is low,my o/p changes once.How can i resolve this ?

Attached is a snapshot to understand it better.

fsm_timing_issue.PNG
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Explorer
Explorer
7,397 Views
Registered: ‎06-25-2014

I would say either...

 

 

1) Don't register your counter in stm.. or...

 

2) Add a register delay to the ready signal to align it with counter and use this as your ready signal

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