04-07-2016 06:19 AM - edited 04-07-2016 06:35 AM
I am trying to debug a problem for our MIG.
Part nos is xc7a100t_1 + Vivado 2015.4.
The above part number is used in our custom board having 4GB DDR memory. Using the exact configurations, no problem is seen at the simulation level. When the same synth test-bench + example design is bit-streamed into our FPGA on the board having the above part, PHY Initialization and Calibration completes successfully. Then problem is seen during compare data stage.
When I set the ILA trigger dbg_cmp_data_valid == 1, and then run, the trigger waits for ever. This is because this signal never becomes HIGH. I see the 64 bit dbg_cmp_data_r to be always 0s. One can also see that dbg_tg_compare_error is always HIGH from the beginning.
However dbg_rddata_r always has valid data. Please see the attached screenshot.
Regardless of the values for the debug signals Used for Configuring the Traffic Generator the above is observed.
Where can the problem be? How can I debug?
04-08-2016 04:56 AM - edited 04-08-2016 04:57 AM
After our board was built and came to us for testing, then with an older ver of Vivado & older IP cores, the example design with the test-bench was working fine. Unfortunately the older ver of Viv was uninstalled.
In the 2015.4 many of the IPs were upgraded and it was automatically done by the tool for this project. Now we have the problem described above. In my opinion there is something wrong with the read data comparison engine.
04-14-2016 03:43 AM - edited 04-14-2016 03:44 AM
Using doc Xilinx_Answer_43879_debug.pdf, I have performed the 'Debugging Data Errors' and 'Determining If a Data Error is Due to the Write or Read'. But I have lack a comparision since dbg_cmp_* signals are all 0/0s whith the dbg_tg_compare_error always being HIGH. I don't know how to proceed or debug further!