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arash9k
Adventurer
Adventurer
3,371 Views
Registered: ‎02-12-2013

Ultrascale DDR3 MIG using "half" of the data and strobe buses only

I need to instantiate a MIG controller (DDR3 SODIMM) for an Ultrascale FPGA. The intended memory part is MT16KTF1G64HZ-1G9P1. This part is already included in the MIG predefined part which is great. However, only 4GB out of the 8GB of this SODIMM is intended for use, as a result, only 32 bits out of the 64 data bits (and 4 out of the 8 strobe bits) are actually connected to FPGA pins. I tried grounding the unused (unconnected) pins in the design but MIG doesn’t allow me and requires that all the pins be connected to the FPGA. Could anyone please recommend a (or maybe some) way(s) / workaround(s) we can get this working?

 

Any tips / tricks / suggestions is highly appreciated.

 

Thanks!

 

PS. I'm working on Vivado 2016.3 but I can use any version of Vivado if I have to.

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vemulad
Xilinx Employee
Xilinx Employee
3,267 Views
Registered: ‎09-20-2012

Hi @arash9k

 

I think Ultrascale MIG IP cannot be generated/used with this setup.

Thanks,
Deepika.
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