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joancab
Scholar
Scholar
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Registered: ‎05-11-2015

Ultrascale Memory Bank/ Byte Planner

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When using the mentioned tool, what are the rules to assign signals within each byte? Can they be swapped just respecting the differential pairs or are there any other restrictions?

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kshimizu
Xilinx Employee
Xilinx Employee
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Registered: ‎03-04-2018

Hello @joancab ,

 

Please refer to the PG150, especially PCB Guidelines for DDR_x.  As for the DDR4, it mentions from page.104.

https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

 

UG583 says the Guideline for Memory Interface in Chapter 2, page.50.

https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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kshimizu
Xilinx Employee
Xilinx Employee
518 Views
Registered: ‎03-04-2018

Hello @joancab ,

 

Please refer to the PG150, especially PCB Guidelines for DDR_x.  As for the DDR4, it mentions from page.104.

https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

 

UG583 says the Guideline for Memory Interface in Chapter 2, page.50.

https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

-------------------------------------------------------

Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

-------------------------------------------------------

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joancab
Scholar
Scholar
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Registered: ‎05-11-2015

 

In my case is DDR3, so page 91 onwards in pG150

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