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Visitor adw10000
Visitor
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Registered: ‎07-13-2019

User interface in MIG

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Hello. my name is john. I want to R/W DDR4 using user interface in MIG.

In PG150, they said about parameter named 'ui_clk' in user interface section that 'ui_clk' must be one quarter of the DRAM clock.

But in my simulation, that signal is not quarter of the DRAM clock. (DRAM clock is 300Mhz, you can see waveform that i upload)

I think something is wrong..

And i have a question about user interface..

Q1. In the picture that i upload, you can see that app_ref_req with system clk... this system clk is equal to ui_clk?

Q2. Is there any good method to do user interface without using traffic generator?

DDR4 simulation waveform.JPGPG150.JPGQ1.JPG

Thanks again and have a good day...

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-21-2007

回复: User interface in MIG

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Yes,the 'ui_clk' is one quarter of the DRAM clock (ddr4_ck in the simualtion, not the system clock input). In Figure 4-8, the system clock means the clock for user interface-> ui_clk.

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Xilinx Employee
Xilinx Employee
231 Views
Registered: ‎08-21-2007

回复: User interface in MIG

Jump to solution

Yes,the 'ui_clk' is one quarter of the DRAM clock (ddr4_ck in the simualtion, not the system clock input). In Figure 4-8, the system clock means the clock for user interface-> ui_clk.