I am trying to connect three AXI4 slave interfaces to xilinx mig_7_series interface generator in a block design using Xilinx axi_interconnect. I instantiated axi_interconnect with configuration of 3 slave and 1 master, (AXI_INT_1) . Two slave interfaces are coming from external interfaces and I set the ID widths to 4. The third slave interface is from another AXI4 Master that utilizes another axi interconnect,(AXI_INT_0). The master interface from AXI_INT_0 has ID width of 4. When I connect the master interface of AXI_INT_1 to the mig_7_series slave interface connection, save the BD, and validate the design, the ID widths of the mig_7_series AXI connection increase to 18. The tool throws an error stating largest ID supported is 16. I have three slave interfaces connected through the interconnect. Why are the ID widths changing to 18 bit? The attached document shows the existing BD,(FROM), and what happens after I try to validate the BD, (TO). Updating the mig.prj file to force the ID to 5:0 results in error when I try to regenerate the BD.