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Visitor
Visitor
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Registered: ‎02-10-2014

Using BRAM as a MCB proxy for development

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I'm in the process of bringing up a board that uses the MCB to connect a Spartan-6 (LX45) to a DDR3 memory. Unfortunately, a few hardware changes have been neccessary. So while I'm waiting for board fabrication and assembly, I'd like to test the behavior of the rest of my system with a BRAM taking the place of the MCB's underlying interface to external memory.

 

Creating this MCB proxy shouldn't require too much adaptation (addition of cmd, wr, and rd queues; handling instructions and BL; etc), but I wanted to check in with the community to see if anyone's tried something similar. I realize I won't be able to have the same memory capcity (kBytes with BRAM versus Gbits with DDR3), but are there any compelling reasons not to pursue this line of development?

 

Thanks in advance for any feedback.

 

Regards,

Drew

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

HI,

 

You can emulate MCB with FIFO but i do not think you will have the same latencies, overhead etc.,

As you do not have the board why can't you for a behavioral simulation?

MIG provides synthesizable test bench and memory models, please go through UG388 , generate the IP and run sim.do or isim.bat in example_design/sim folder, also if you run create_ise.bat in example_design/par folder  you will be knowing the hierarchy, later you can just replace traffic gen with your own write or read interface.

 

http://www.xilinx.com/support/answers/37424.htm

 

http://www.xilinx.com/support/answers/43162.html

 

 

Hope this helps

 

Regards,

Vanitha

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Xilinx Employee
Xilinx Employee
15,286 Views
Registered: ‎07-11-2011

HI,

 

You can emulate MCB with FIFO but i do not think you will have the same latencies, overhead etc.,

As you do not have the board why can't you for a behavioral simulation?

MIG provides synthesizable test bench and memory models, please go through UG388 , generate the IP and run sim.do or isim.bat in example_design/sim folder, also if you run create_ise.bat in example_design/par folder  you will be knowing the hierarchy, later you can just replace traffic gen with your own write or read interface.

 

http://www.xilinx.com/support/answers/37424.htm

 

http://www.xilinx.com/support/answers/43162.html

 

 

Hope this helps

 

Regards,

Vanitha

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Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

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Visitor
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Registered: ‎02-10-2014

Hi Vanitha,

 

Thanks for pointing out the MCB's example design / simulation testbench. I've used this resource in the past to help design and verify the behavior of different aspects of my project (using ISim / ModelSim). My goal is to create a synthesizable alternative (same interface behaviorally) to the fully-fledged Memory Control Block while I address an SI/Layout issue between the FPGA and DDR3 memory. This will allow my colleagues and I to start integrating components of our project -- already designed to work with the MCB FIFO interface -- that use the FPGA to bridge communications without waiting for another hardware iteration.

 

I'm in the middle of testing my first attempt at this "BRAM as MCB proxy" using ChipScope. I'll post an update in the near future.

 

=Drew

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