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Visitor summerweix
Visitor
150 Views
Registered: ‎10-05-2019

Using both DDR on VCU118 Board

Hi,

I'm trying to use both ddr4 sdram c1 and ddr sdram c2 on VCU118 board. However, during implementation the following errors showed up for the one using ddr sdram c2, do you have any suggestion how to sovle this?

 

mig core fail.PNG
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Xilinx Employee
Xilinx Employee
71 Views
Registered: ‎01-09-2019

Re: Using both DDR on VCU118 Board

Hello @summerweix 

The error talks about the I/O placement that you have.  In particular you need to all the I/O for each controller in the same SLR.  Did you try using the Byte Planner?

The required pin placement rules for the PL memory IP can be found in PG150.  The DDR4 pin rules start on page 104 and will all need to be adhered to in order to pass the DRCs and implement properly.

I think your pin planning put some of the pins in Bank 71 where those should have been in Bank 43 to stay completely in SLR 0.  I would need to see the full pin planning to know any more.

Thanks,
Caleb
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