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Adventurer
Adventurer
26,150 Views
Registered: ‎03-05-2009

V6 240T and MIG : Need Help Please !

Hello,

 

I have a Virtex 6 Hitech Global developement Board (V6Board), which use a XC6vlx240T-2 and 1Gb of DDR3.

 

I have tried to use this external DDR3 for Days with no success... Also I am asking for help please....

 

Here is he pinout of my V6Board : BOARD.UCF

 

Will trying to generate a mig_v3_6 component with the core generator, I defined the mig options using a "reference design" hitec global gives with the board (mig.prj and reference project)

 

I also tried to add this reference design to my ise project, but i have errors and no way to "regenerate it"...

 

I do not know how to do, help me please !

 

thank you,

 

Alex

 

 

 

 

 

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8 Replies
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Scholar
Scholar
26,142 Views
Registered: ‎02-27-2008

Alex,

 

http://www.hitechglobal.com/contactus.htm

 

You need to talk to the people who support the product you bought....

Austin Lesea
Principal Engineer
Xilinx San Jose
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Voyager
Voyager
26,114 Views
Registered: ‎05-21-2008

MIG tool does not generate reference design of your board directly. You need to generate a MIG core with your pin out file or contact your vendor to get a reference design.
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Adventurer
Adventurer
26,111 Views
Registered: ‎03-05-2009

I managed to generate a MIG with the good outputs / specifications.

But when i synthesis the ISE project, I got black boxes and then NgdBuild:604 errors...

 

Here is an example :

 

 

ERROR:NgdBuild:604 - logical block 'uu_mig_v3_6/gen_dbg_enable.u_cs3' with type
   'vio_async_in256' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'vio_async_in256' is not supported in target 'virtex6'.

 

 

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Xilinx Employee
Xilinx Employee
26,094 Views
Registered: ‎01-03-2008

The error message is related to the design including a ChipScope VIO (Virtual I/O) core, but NGDBUILD could not find the module (vio_async_in256) in the project or search path.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Adventurer
Adventurer
26,090 Views
Registered: ‎03-05-2009

I do not use chipscope...

 

I have other errors also :

 

 

Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -intstyle ise -dd _ngo -sd mig_v3_6 -sd mig_v3_6/user_design -sd mig_v3_6/user_design/par -nt timestamp -uc DDR3_ISE.ucf -p xc6vlx240t-ff1759-2 "DDR3_ISE.ngc" DDR3_ISE.ngd

Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
ise -dd _ngo -sd mig_v3_6 -sd mig_v3_6/user_design -sd mig_v3_6/user_design/par
-nt timestamp -uc DDR3_ISE.ucf -p xc6vlx240t-ff1759-2 DDR3_ISE.ngc DDR3_ISE.ngd

Reading NGO file "D:/Projets/Hyb RX/VHDL/DDR3_New/DDR3_ISE.ngc" ...
Loading design module "D:\Projets\Hyb RX\VHDL\DDR3_New/fif_v7_2.ngc"...
Applying constraints in "D:\Projets\Hyb RX\VHDL\DDR3_New/fif_v7_2.ncf" to module
"D:\Projets\Hyb RX\VHDL\DDR3_New/fif_v7_2.ngc"...
Checking Constraint Associations...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "DDR3_ISE.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...






Done...

Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'uu_mig_v3_6/gen_dbg_enable.u_icon' with type
   'icon5' could not be resolved. A pin name misspelling can cause this, a
   missing edif or ngc file, case mismatch between the block name and the edif
   or ngc file name, or the misspelling of a type name. Symbol 'icon5' is not
   supported in target 'virtex6'.
ERROR:NgdBuild:604 - logical block 'uu_mig_v3_6/gen_dbg_enable.u_cs3' with type
   'vio_async_in256' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'vio_async_in256' is not supported in target 'virtex6'.
ERROR:NgdBuild:604 - logical block 'uu_mig_v3_6/gen_dbg_enable.u_cs2' with type
   'vio_async_in256' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'vio_async_in256' is not supported in target 'virtex6'.
ERROR:NgdBuild:604 - logical block 'uu_mig_v3_6/gen_dbg_enable.u_cs1' with type
   'vio_async_in256' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'vio_async_in256' is not supported in target 'virtex6'.
ERROR:NgdBuild:604 - logical block 'uu_mig_v3_6/gen_dbg_enable.u_cs4' with type
   'vio_sync_out32' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'vio_sync_out32' is not supported in target 'virtex6'.
ERROR:NgdBuild:604 - logical block 'uu_mig_v3_6/gen_dbg_enable.u_cs0' with type
   'ila384_8' could not be resolved. A pin name misspelling can cause this, a
   missing edif or ngc file, case mismatch between the block name and the edif
   or ngc file name, or the misspelling of a type name. Symbol 'ila384_8' is not
   supported in target 'virtex6'.
ERROR:NgdBuild:770 - IBUFG
   'uu_mig_v3_6/u_iodelay_ctrl/se_clk_ref.u_ibufg_clk_ref' and BUFG
   'uut/U_FBclk' on net 'Clk_200' are lined up in series. Buffers of the same
   direction cannot be placed in series.
ERROR:NgdBuild:924 - input pad net 'Clk_200' is driving non-buffer primitives:
     pin C on block Start_rd_A with type FDC,
     pin C on block FIFO_Threshold with type FDC,
     pin C on block App_en with type FDC,
     pin C on block App_wdf_end with type FDC,
     pin C on block Start_wr_A with type FDC,
     pin C on block App_wdf_data_0 with type FDC,
     pin C on block App_wdf_data_1 with type FDC,
     pin C on block App_wdf_data_2 with type FDC,
     pin C on block App_wdf_data_3 with type FDC,
     pin C on block App_wdf_data_4 with type FDC,
     pin C on block App_wdf_data_5 with type FDC,
     pin C on block App_wdf_data_6 with type FDC,
     pin C on block App_wdf_data_7 with type FDC,
     pin C on block App_wdf_data_8 with type FDC,
     pin C on block App_wdf_data_9 with type FDC,
     pin C on block App_wdf_data_10 with type FDC,
     pin C on block App_wdf_data_11 with type FDC,
     pin C on block App_wdf_data_12 with type FDC,
ype FDC,
     pin C on block App_wdf_data_14 with type FDC
ERROR:NgdBuild:770 - IBUFG 'uu_mig_v3_6/u_clk_ibuf/se_input_clk.u_ibufg_sys_clk'
   and BUFG 'uut/U_clk533' on net 'Clk_533M' are lined up in series. Buffers of
   the same direction cannot be placed in series.
ERROR:NgdBuild:924 - input pad net 'Clk_533M' is driving non-buffer primitives:
     pin O on block uut/U_clk533 with type BUFG
     pin C on block App_wdf_data_13 with tWARNING:NgdBuild:452 - logical net 'N904' has no driver
WARNING:NgdBuild:452 - logical net 'N905' has no driver
WARNING:NgdBuild:452 - logical net 'N906' has no driver
WARNING:NgdBuild:452 - logical net 'N907' has no driver
WARNING:NgdBuild:452 - logical net 'N908' has no driver
WARNING:NgdBuild:452 - logical net 'N909' has no driver
WARNING:NgdBuild:452 - logical net 'N910' has no driver
WARNING:NgdBuild:452 - logical net 'N911' has no driver
WARNING:NgdBuild:452 - logical net 'N912' has no driver
WARNING:NgdBuild:452 - logical net 'N913' has no driver
WARNING:NgdBuild:452 - logical net 'N914' has no driver
WARNING:NgdBuild:452 - logical net 'N915' has no driver
WARNING:NgdBuild:452 - logical net 'N916' has no driver
WARNING:NgdBuild:452 - logical net 'N917' has no driver
WARNING:NgdBuild:452 - logical net 'N918' has no driver
WARNING:NgdBuild:452 - logical net 'N919' has no driver

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:    10
  Number of warnings:  16

Total REAL time to NGDBUILD completion:  22 sec
Total CPU time to NGDBUILD completion:   20 sec

One or more errors were found during NGDBUILD.  No NGD file will be written.

Writing NGDBUILD log file "DDR3_ISE.bld"...

Process "Translate" failed

 

 

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Xilinx Employee
Xilinx Employee
26,077 Views
Registered: ‎01-03-2008

> I do not use chipscope...

 

You may think that you aren't using ChipScope, but your log files say otherwise.

 

Chipscope ICON core:

ERROR:NgdBuild:604 - logical block 'uu_mig_v3_6/gen_dbg_enable.u_icon' with type

   'icon5

 

Chipscope VIO core:

ERROR:NgdBuild:604 - logical block 'uu_mig_v3_6/gen_dbg_enable.u_cs3' with type
   'vio_async_in256'

 

Chipscope VIO Core:

ERROR:NgdBuild:604 - logical block 'uu_mig_v3_6/gen_dbg_enable.u_cs4' with type
   'vio_sync_out32'

 

ChipScope ILA Core:

ERROR:NgdBuild:604 - logical block 'uu_mig_v3_6/gen_dbg_enable.u_cs0' with type
   'ila384_8'

 

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Xilinx Employee
Xilinx Employee
25,989 Views
Registered: ‎11-29-2009

Hi,

 

I think during MIG core generation you might have enabled debug option switch and that inserts chipscope.

 

Try generating the core with debug disable and see if that works fine.

 

Thanks

Satyakumar

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Visitor
Visitor
25,287 Views
Registered: ‎10-08-2010

Hi~  You can run ise_flow.bat generated by core generator. Then add the "icon5_cg.xco"  "ila384_8_cg.xco"  "vio_async_in256_cg.xco"  "vio_sync_out32_cg.xco" to your ise project.

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