UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer slee777
Observer
592 Views
Registered: ‎06-18-2018

VCU128 DDR4 Memory IP troubleshoot in Vivado 2018.3

Jump to solution

Hi,

When building for VCU128 HBM board, the DDR4 IP selects the memory part MT40A512M16HA-075E even though the schematic says it is using MT40A512M16LY-075E. Will it cause any difference to building the project? In addition, with the VCU128 board setting, DDR4 IP requires 17 bit DDR4 address but schematic/xdc pinout only has 14 bits, causing opt design error stating "[Mig 66-99] Memory Core Error - [design_1/ddr4_0] MIG Instance port(s) c0_ddr4_adr[14], c0_ddr4_adr[15], c0_ddr4_adr[16] ... are not connected to top level instance of the design". Is this expected? Is there workaround?

Screenshot_2019-02-12_14-50-01.png
0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
537 Views
Registered: ‎11-28-2016

Re: VCU128 DDR4 Memory IP troubleshoot in Vivado 2018.3

Jump to solution

Hello @slee777,

Based on that description this is a dual rank clamshell topology so when you configure the DDR4 controller you need to check the box for Clamshell Topology.  This will generate the two CS signals where CS0 goes to CS_B and CS1 goes to BOT_CS_B.

clamshell.PNG

View solution in original post

3 Replies
Moderator
Moderator
553 Views
Registered: ‎11-28-2016

Re: VCU128 DDR4 Memory IP troubleshoot in Vivado 2018.3

Jump to solution

Hello @slee777,

Those DDR4 parts are functionally identical in this application.  The difference between the two parts, MT40A512M16HA-075E and MT40A512M16LY-075E, is simply the package code which has no operational impact on the devices.  The base part, an 8Gbit DDR4 component comprised of 16-DQ bits x 512M deep with a -075E speed grade are identical.

Now for the pinout I'm looking at the VCU128 user guide UG1302 linked here:
https://www.xilinx.com/support/documentation/boards_and_kits/vcu128/ug1302-vcu128-eval-bd.pdf
In Table 6 it talks about one of the DDR4 interfaces and I noticed that it uses the functional names for address 14, 15, and 16 as PL_DDR4_WE_B, PL_DDR4_CAS_B, and PL_DDR4_RAS_B since the address pins also function as WE, CAS, and RAS.  For the chip select pin, from what I can tell, there's only 1 CS signal required since this is operating as a single rank clamshell topology, so the IP doesn't require a c0_ddr4_cs_n[1] signal.

Observer slee777
Observer
542 Views
Registered: ‎06-18-2018

Re: VCU128 DDR4 Memory IP troubleshoot in Vivado 2018.3

Jump to solution

Hi @ryana,

I've gotten passed the DDR4 address, but the DDR4 IP will error out if c0_ddr4_cs_n[1] is not connected. Where should it be connected to?

I looked at the xdc file provided and schematic, and notice that there's two cs_n coming from the FPGA, PL_DDR4_BOT_CS_B and PL_DDR4_CS_B. In page 25 of VCU128 schematic, both of these signals are connected to DD4 chip select. Which one should be connected to ddr4_sdram_cs_n[0] and which one should be connected to ddr4_sdram_cs_n[1]?

Thanks,

Screenshot from 2019-02-13 15-39-03.png
0 Kudos
Moderator
Moderator
538 Views
Registered: ‎11-28-2016

Re: VCU128 DDR4 Memory IP troubleshoot in Vivado 2018.3

Jump to solution

Hello @slee777,

Based on that description this is a dual rank clamshell topology so when you configure the DDR4 controller you need to check the box for Clamshell Topology.  This will generate the two CS signals where CS0 goes to CS_B and CS1 goes to BOT_CS_B.

clamshell.PNG

View solution in original post