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Mentor
Mentor
509 Views
Registered: ‎06-09-2011

Virtex-6 MIG DDR2 unroutable signals

Hi all,

I am working on a custom board based on Virtex-6. I wanted to use MIG core for DDR2 SDRAM connected to my FPGA. I have followed all the instructions and steps for core wizard. Unfortunately, I am receiving below errors and can't go further:

ERROR: Route:471 -
This design is unrouteable. Router will not continue. To evaluate the problem please use fpga_editor. The nets listed below can not be routed:

Unrouteable
Net:MyPulseGen_INST/MyFirstDdr_INST/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1].u_phy_dqs_iob/u_iobuf_dqs/IBUFDS/SLAVEBUF.DIFFIN


Unrouteable
Net:MyPulseGen_INST/MyFirstDdr_INST/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1].u_phy_dqs_iob/u_iobuf_dqs/IBUFDS_0/SLAVEBUF.DIFFIN


Unrouteable
Net:MyPulseGen_INST/MyFirstDdr_INST/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[1].u_phy_dqs_iob/u_iobuf_dqs/split_buf_net


Unrouteable
Net:MyPulseGen_INST/MyFirstDdr_INST/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0].u_phy_dqs_iob/u_iobuf_dqs/IBUFDS/SLAVEBUF.DIFFIN


Unrouteable
Net:MyPulseGen_INST/MyFirstDdr_INST/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0].u_phy_dqs_iob/u_iobuf_dqs/IBUFDS_0/SLAVEBUF.DIFFIN


Unrouteable
Net:MyPulseGen_INST/MyFirstDdr_INST/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_data_io/gen_dqs[0].u_phy_dqs_iob/u_iobuf_dqs/split_buf_net

 As I looked further into generated HDL codes like phy_dqs_iob.vhd module - the first generated error above - I see that it is using a module named iobuf_dqs and also a device primitive named

IOBUFDS_DIFF_OUT which comes below:

 

u_iobuf_dqs: IOBUFDS_DIFF_OUT
generic map (
IBUF_LOW_PWR => IBUF_LOW_PWR
)
port map (
o => dqs_ibuf_p,
ob => dqs_ibuf_n,
io => ddr_dqs_p,
iob => ddr_dqs_n,
i => dqs_p_iodelay,
tm => dqs_p_tq,
ts => dqs_n_tq
);

Unfortunately, I couldn't find a primitive named IOBUFDS_DIFF_OUT in the list of Virtex-6 primitives. That's why I think it can't route these signals. There isn't such resource inside Virtex-6. Or, another primitive - IBUFDS - doesn't have pin like SLAVEBUF.DIFFIN.

I took a look at the definition of IBUFDS :

IBUFDS_inst : IBUFDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => O, -- Buffer output
I => I, -- Diff_p buffer input (connect directly to top-level port)
IB => IB -- Diff_n buffer input (connect directly to top-level port)
);

I am wondering why such primitives have been used during the HDL code generation? I have to add that I have checked the core wizard so many times and I am choosing correct device and every other things.

I would appreciate any help,

Hossein

Thanks,
Hossein
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2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
476 Views
Registered: ‎08-21-2007

Did you modify the ucf accroding your board after the IP core was generated?

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Highlighted
Mentor
Mentor
467 Views
Registered: ‎06-09-2011

Hi

I had specified all pin locations in ucf file. Is there anything else that needs to be defined?

Thanks,

Hossein

Thanks,
Hossein
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