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Observer
Observer
8,100 Views
Registered: ‎02-10-2011

Vivado 2015.1 MIG 7 series generate timing problems for Atrix 7 xc7100tfgg484-3

I get timing constraint problem by using MIG in block design for DDR3 memory and  Atrix 7 xc7100tfgg484-3 device.

input clock 200 MHz  DDR3 ram clock 400 MHz

Have tryed different implementation strategy without sucsess.

How to resolve?

 

MIG-DDR3.jpg
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Xilinx Employee
Xilinx Employee
8,095 Views
Registered: ‎07-11-2011

Hi,

 

Have you modified any MIG clocking architecture or constraints or RTL after the IP generation? If yes please regenerate the IP usng  "verify pin changes and updat design" radio button option in MIG GUI and rerun the synthesis and implementation flow.

Is this seen only in over all design or example design as well?

If the error occurs in example design  upload your xci and xdc for investigation

If no error is sen in example design, I would suggest you to use Vivado Default Synthesis and Implementation settings used by example design and recheck.

 

-Vanitha.

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Observer
Observer
7,997 Views
Registered: ‎02-10-2011

Hi,

Regenerated without success. Have still timing problems on ddr3_dqs_p[0] to mmcm_ps_clk_bufg_in  and ddr3_dqs_p[1] to mmcm_ps_clk_bufg_in. This signals is copleated generated by the MIG.

 

I don't have any reference design, I started from scratch generating a block design.

then used the wrapper, the block is connected to my top design written in VHDL.

Enclodsed the block design.

Thanks.

Anders

Block-design.jpg
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