06-15-2015 01:56 AM
I get timing constraint problem by using MIG in block design for DDR3 memory and Atrix 7 xc7100tfgg484-3 device.
input clock 200 MHz DDR3 ram clock 400 MHz
Have tryed different implementation strategy without sucsess.
How to resolve?
06-15-2015 02:04 AM - edited 06-15-2015 08:46 AM
Have you modified any MIG clocking architecture or constraints or RTL after the IP generation? If yes please regenerate the IP usng "verify pin changes and updat design" radio button option in MIG GUI and rerun the synthesis and implementation flow.
Is this seen only in over all design or example design as well?
If the error occurs in example design upload your xci and xdc for investigation
If no error is sen in example design, I would suggest you to use Vivado Default Synthesis and Implementation settings used by example design and recheck.
06-23-2015 04:11 AM
Regenerated without success. Have still timing problems on ddr3_dqs_p to mmcm_ps_clk_bufg_in and ddr3_dqs_p to mmcm_ps_clk_bufg_in. This signals is copleated generated by the MIG.
I don't have any reference design, I started from scratch generating a block design.
then used the wrapper, the block is connected to my top design written in VHDL.
Enclodsed the block design.