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efpkopin
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Registered: ‎01-20-2017

WE_N to DQS delay must equal CWL

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I'm implementing a MIG between a Kintex 7 FPGA and a single DDR3 chip.  In UG586 (June 8, 2016), on page 255 related to debugging write calibration failures, it says:

The WE_N to DQS delay must equal the CAS Write Latency (CWL)

The bullet suggests we measure the delay in time between rising edges of WE_N and DQS.  However the CWL is given in the MIG configuration as a single number (in our case it is '11')  What does this CWL number represent in terms of time.  Is it number of memory clock cycles?  And are we supposed to set the trace lengths such that the WE_N is longer than the DQS signals by a length calculated as:    CWL*memory_clock_period*propagation_rate

 

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kren
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Registered: ‎08-21-2007

Yes, the CWL is caculated in number of memory clock cycles. 

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kren
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Registered: ‎08-21-2007

Yes, the CWL is caculated in number of memory clock cycles. 

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efpkopin
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Registered: ‎01-20-2017

Actually, I have a follow-up to this question (I'm not sure if I should start another topic - please let me know if I should):

The bullet point on page 255 says the 'WE_N to DQS delay must equal the CAS Write Latency (CWL).'  In my memory controller, I have an 800 MHz DDR memory clock (1.25 ns period) and the 'CAS Latency' in the design report is 11.  It seems strange that you'd want the delay between these two memory signals to be equal to 11 clock periods (13.75 ns). 

The other confusing part is that on or around page 199 of this same document (UG586), it says:

1. The optimal delay between the clock signal and any address/control signals (I consider WE_N one of these control signals) to be 8 ps.

2. The recommended delay that CK signals should arrive after the DQS signals is between 150 ps and 1600 ps. 

So taking these two statements, the spec says it is acceptable for the WE_N signal to arrive after DQS as close as 158 ps (8 ps + 150 ps).  So this is obviously much faster than 11 memory clock periods.  

What am I getting wrong?

 

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