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Registered: ‎09-15-2014

Why both Vref and VTT are pulled low (0.9V -> 0.28V) once MIG-design is downloaded to the XC5VSX95T

Hi all:

I am recently working around accessing to DDR2 with MIG based DDR2 controller, however, i am quite confused with one symptom:

once the .bit file containing the DDR2 controller is downloaded into XC5VSX95T, both VTT and Vref will drop from 0.9V to approximately 0.28V.


My Configuration:

(1) I have tristated all unused pins when "Generate Programing File"。

(2) The DDR2-SDRAM and all the relevant BANKs are powered by TPS51116, a specific power-regulator that provides

      sources (VTT_0V9, Vref_0V9, and VCC_1V8) to DDR2. According to the data-sheet, VTT generated by TPS51116

      is capable of both SINKING and SOURCING (3A current is allowed @ VTT per direction).

(3) During configuration of MIG, i haved selected the "Fixed Pins" option, but, the generation is successful with no errors

      being reported.


Things that i have verified:

(1) Pin assignment is completely correct. I have double checked this.

(2) UCF regarding DDR2 is copied from the MIG-generated demo "The directory: ipcores->ddr2->user->par".

(3) Hardware is correctly connected.


The main issue to resolve:

phy_init_done is always deasserted (always stays LOW), and i guess the main reason for phy_init_done not being asserted lies in that, Vref drops from 0.9V to 0.28V (Note that Vref is the reference voltage in SSTL-18).

From chipscope, it can be clearly observed that the calibration process stucked somewhere between "CALIB_READ" and "CALIB_WRITE".



Please help.....

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4 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎07-31-2012



The reduction in the voltage level is probably because the current requirement is not getting satisfied by the power source or the decoupling capacitors are not as per spec.


Did you check the current requiirement in XPA or XPE and select your power source accordinngly for your design. Also check the Packaging user guide for the docpuling capacitor requirements for the power sources for your device.


PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Xilinx Employee
Xilinx Employee
Registered: ‎07-11-2011




For debugging calibration failure go through Section VI: Debug Guide of UG086 and do a a step by step investigation


For possible causes of vref drop please visit relavant discusisons and follow the suggestions






Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
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Registered: ‎09-15-2014

Hi athandr: I have removed all the parallel termination resistors, which were connected as shown in the following figure


Thus, now, VTT_DDR2 has no load at all (it connects nothing once the parallel resistors are removed).

Still, i measured that Vref drops form 0.9V to 0.28V once MIG is downloaded into XC5VSX95T.


Let's be clear:

(1) I can verify that all unused pins are indeed tristated when "generating programming file".

(2) VTT are fully disconnected, it connects nothing.

(3) Vref pins are correctly connected to the VREF-PINS of the MIG-Correlated BANKs of SX95T, which is also verified

      by the pin report generated by ISE.


So My Explanation:

SX95T drives the IO_XXXX_VREF pins internally!!!!!!!!!!!!


My Proof to this:

i.     Vref source from TPS51116 is only connected to Vref pins of DDR2-SDRAM and FPGA.

ii.    Upon powerring up, FPGA is not configured and All Vref and VTT(VTT is disconnected now) are 0.9V.

iii.   Once MIG is downloaded, Both VTT and Vref drops from 0.9V  to 0.28V...


Can anybody show how this could happen??????????????????


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Registered: ‎09-15-2014

Hi vsrunga,
your solution is concerning Virtex-6 series. my FPGA is XC5VSX95T. And the most important thing is Vref for V5 and V6 differs in terms of MIG...
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