UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
490 Views
Registered: ‎01-18-2011

Write error via the User Interface

Jump to solution

Hello

 

I use ISE 14.7, 7 Series FPGA, MIG v1.9 and DDR3 memory model .

Memory controller works in 4:1 mode with BL=8. I try to write to the memory. And I see zeros on the memory data bus instead of the my first burst of 128 bits. The next writes are correct. What is the reason of this? Is my timing diagram right?

1.jpg
0 Kudos
1 Solution

Accepted Solutions
Explorer
Explorer
647 Views
Registered: ‎01-18-2011

Re: Write error via the User Interface

Jump to solution

I'm sorry. I forgot to apply SYS_RST at the beginning of simulation.

1 Reply
Explorer
Explorer
648 Views
Registered: ‎01-18-2011

Re: Write error via the User Interface

Jump to solution

I'm sorry. I forgot to apply SYS_RST at the beginning of simulation.