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Visitor lsisaxon
Visitor
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Registered: ‎03-06-2018

XCZU3EG LPDDR4 routing question

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Hi,

 

In the UG1075 document, the rules for LPDDR4 pin swapping is mentioned. ie, DQ lane swapping is not allowed, DQ bits with bytes 0, 2 and 8 are not swappable, bits within byte 1 and 3 can be swapped.

 

Is my understanding correct that DQ0~DQ7, DQ16~DQ23 cannot be swapped but it is possible for DQ8~DQ15 and DQ24~DQ31?

 

In such a situation, does it also mean that I actually have to keep DQ0~DQ15 as  a group and DQ16~DQ31 as another, in terms of trace length/routing layer? Or can they be broken into 4 groups of 8 bits, DQ0~DQ7, DQ8~DQ15, DQ16~DQ23 and DQ24~DQ31 and it is only sufficient that I maintain the skew constraints detailed in UG583?

 

Also, for the CKE and CS, in UG583, it is recommended to route the from the controller to Channel A and then chained to Channel B. Is it also possible to route as a T and branching out equidistant to Channel A and Channel B? Will there be an impedance issue if I keep the lines short?

 

Also for the CKE, are the 160 ohm termination resistors to VDDQ and GND or 80ohm to VDDQ necessary?

 

Thank you.

 

Best regards,

Saxon

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Moderator
Moderator
1,077 Views
Registered: ‎11-28-2016

Re: XCZU3EG LPDDR4 routing question

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Hello @lsisaxon,

 

For question 1, yes, that's correct.  From the LPDDR4 guidelines in UG1075 you cannot swap bits within bytes 0, 2, and 8 (ECC) but you are allowed for bytes 1 and 3. 

 

The guideline in UG583 is that all the data bits, the data mask, and the DQS for a byte need to be routed together on the same layer.  The restriction of swapping bits within a byte is talking about mapping PS_DDR_DQ0 to DQ_7 on the LPDDR4. This means that bytes 0, 2, and 8 need to have 1:1 mapping to their respective PS_DQ bit to the DQ bit on the LPDDR4.

 

Your interpretation is correct that you can route them separately as 4 groups as long as you meet the skew requirements (as well as all of the other requirements) in UG583.  They don't need to be routed together as DQ0-DQ15 and DQ16-DQ31.

 

For the CKE and CS signals the guidline is to route them as fly-by to Channel A first and Channel B second.  T-Branch is not recommended because of the signal integrity issues that causes and it's not a tested or characterized configuration so you'll be on your own to evaluate the potential pitfalls with this type of layout.

 

Yes, for CKE you must have one of those two topologies on your board for the device to work.

 

 

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Moderator
Moderator
1,078 Views
Registered: ‎11-28-2016

Re: XCZU3EG LPDDR4 routing question

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Hello @lsisaxon,

 

For question 1, yes, that's correct.  From the LPDDR4 guidelines in UG1075 you cannot swap bits within bytes 0, 2, and 8 (ECC) but you are allowed for bytes 1 and 3. 

 

The guideline in UG583 is that all the data bits, the data mask, and the DQS for a byte need to be routed together on the same layer.  The restriction of swapping bits within a byte is talking about mapping PS_DDR_DQ0 to DQ_7 on the LPDDR4. This means that bytes 0, 2, and 8 need to have 1:1 mapping to their respective PS_DQ bit to the DQ bit on the LPDDR4.

 

Your interpretation is correct that you can route them separately as 4 groups as long as you meet the skew requirements (as well as all of the other requirements) in UG583.  They don't need to be routed together as DQ0-DQ15 and DQ16-DQ31.

 

For the CKE and CS signals the guidline is to route them as fly-by to Channel A first and Channel B second.  T-Branch is not recommended because of the signal integrity issues that causes and it's not a tested or characterized configuration so you'll be on your own to evaluate the potential pitfalls with this type of layout.

 

Yes, for CKE you must have one of those two topologies on your board for the device to work.

 

 

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Visitor lsisaxon
Visitor
836 Views
Registered: ‎03-06-2018

Re: XCZU3EG LPDDR4 routing question

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Hi Ryana,

Thanks for the confirmation.

Best regards,
Saxon
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