02-26-2021 02:08 PM
I am using a ZCU111 board and am unable to run the PS from DDR. When I attempt to run a program, it will program the FPGA, and then gets stuck while running the psu_init.tcl. The line it gets stuck on is in the procedure psu_ddr_phybringup_data:
poll 0xFD080030 0x00000FFF 0x00000FFF
If I comment out the psu_ddr_phybringup_data call, psu_init.tcl completes, but either the processor never executes the program, or I get other errors. I can run out of OCM if and only if I comment out the psu_ddr_phybringup_data call.
We have 2 other ZCU111 boards that have never exhibited this issue with same exact design. I have come across a couple of postings where people have had similar issues with their own custom boards, but those turned out to be board issues. There is a forum post with a similar issue with the ZCU102 & ZCU106 boards (AR# 71961) that was caused by a change in the Micron DDR that is used on those boards. I am wondering is this the same type of issue and is there a fix for it.
I am using Vivado 2018.3.
03-02-2021 09:59 PM
The psu_init.tcl has some DDR issues that were not fixed. In later tool versions, it has been removed as part of the debug flow. Try instead to download/run the FSBL from SDK/Vitis first, which compiles in psu_init.c (instead of .tcl), which will better match a deployed design.
03-03-2021 06:32 AM
I've actually tried that. After running the FSBL, I run the design (without running psu_init). It appears to load and the Debug window says Cortex-A53 #0 is running, however, it never actually executes the loaded program. If I hit Suspend, I get an error box with the following:
Cannot suspend: TCF error report:
Command:RunControl suspend "JTAG-jsn-JTAG-HS2-210249ACD5C5-5ab00477-0A0"
Time: 2021-03-03 08:07:26.781
Error text: Cannot halt processor core, timeout