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Anonymous
Not applicable
7,913 Views

Zynq DDR3 customization Issue

Hi,

 

Am generating my design for DDR3 core which is present in PS side using block design in Vivado.

I modified the DDR3 part  to MT41J64M16JT which has 16 bit data width and 14 bit address width.

When I build the design, I am getting 32  data ports and 15 address ports.  Am connecting extra DDR ports as signals, but this can cause failure during DDR initialization.

How to generate the design?

Find the attched design and help me in generating it.

 

Thanks

Vinod

 

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vsrunga
Xilinx Employee
Xilinx Employee
7,905 Views
Registered: ‎07-11-2011

Hi,

 

Try to choose a memory part as base part  that is close to your chip on the board so that you can get the exact nuber of address lines, if you do not really find it you can ground the addiotional address lines at memory  provided they have no role in mode register configuration.

You need to check your memory device datasheet for address lines decoding.

 

Please refer below links as well

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/RLDRAM3/m-p/414479#M5308

 

 

Regards,

Vanitha

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Anonymous
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Hi ,

 

I choosed the exact DDR memory part only but pinouts are extra from ARM PS side.

Actually all Pins are having INOUT directions. So am not able to ground them and even if I connect them as sigals, SYnthesis is failing.

 

Can I connect them to IO's that are unused/unconnected to FPGA ? Is there any other solution?

 

Thanks,

Vinod

 

 

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