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kalhana_oa
Observer
Observer
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Registered: ‎10-31-2018

Zynq Ultrascale+ PS LPDDR4 byte group skew

I'm doing a design with Zynq Ultrascale+ with LPDDR4 on the PS side (I'm using a single 2GB LPDDR4 IC which has dual die and 32-bit bus - Micron MT53D512M32D2DS-046).

In UG583 (v1.18), page 96, Table 2-45 it mentions the skew constraints.

In the 2nd row of the table, it mentions "Data (DQ/DM) to DQS (A)" and "Data (DQ/DM) to DQS (B)" should be ±5ps.

My question is, does this mean that all the data/strobe/mask in channel A (and B) have to be matched as opposed to each byte group separately (16-bit data groups matched in each channel)?

If so, that's harder to do than the usual DDR skew matching where only 8-bit byte groups are separately matched without any dependence between them.

So you end up with 2 groups of 16bit data skew matched as opposed to 4 groups of 8-bit data?

4 Replies
rpr
Moderator
Moderator
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Registered: ‎11-09-2017

Hi @kalhana_oa 

LPDDR4 Channel A and channel B are independent, so there is no skew dependent between them. So you can group bytes of channel A and channel B separately.

Regards
Pratap

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kalhana_oa
Observer
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Registered: ‎10-31-2018

Yes, but channel A has 2 bytes and channel B has 2 bytes. Does this mean both bytes in channel A has to have the same skew?

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wouter81
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Registered: ‎06-17-2015

My expectation: 5ps matching should be done per byte group. This is unclear in the User Guide. Hopefully someone can clear this up. And update ug583.

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dan1
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Registered: ‎07-14-2020

Hi,

Is there an official answer from Xilinx on this issue yet? I am also stuck.

I've attached an image that illustrates my interpretation of Table 2-45 on page 96 of the PCB Design Guide.
Red indicates what is unknown to me, and the confusion is mostly brought about by the 4th row of the table.

Note that I have only drawn a single channel since they are tuned independently.

LPDDR4 Length Matching Skew.png
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