10-18-2011 05:48 AM
I am using
1. Spartan 6 FPGA (LX150T)
2. Memory MT47H32M16HR-25E (2 nos, one in Bank4 and one in Bank5)
I have two doubts
1. I am planning to use MT47H32M16HR-25E (400MHz) which is not there by default in the list of supported devices. So, what I did is, i selected a x16 memory (elpida EDE5116AJBG-8E) as the reference part and made changes as per needed and saved it as MT47H32M16HR-25E. Please tell me if there is anything wrong in what i have done.
2. to use the generated core, I added the .xco file to the project, now if i copy the instantiation template to my code, i can instantiate the generated MCB core. But one doubt, I have read everywhere that the MCB needs two clocks (sysclock_2x and its 180 degree phaseshifted version) which is generated by a PLL, and which should be buffered through BUFPLL_MCB. Now, when I check the instantiation code, there is not sysclock_2x there in it, instead, if i open the HDL functional model for the core, i can see that it in itself has PLLs which is providing the necessary clocks for the MCB
Now the doubt is, for the PLL, an input goes "c5_sys_clk" ("c4_sys_clk" in the case of bank 4 ) which is actually input of the core which has been generated. But, I dont know what is the PLL divider settings created by MIG, then how can i decide on what frequency clock should I connect to "c5_sys_clk" ?
( or should it be like, i have to generate the PLL core separately, and then instantiate the MCB wrappers and connect the clocks manually ? )
10-18-2011 12:35 PM
1. As long as you used Create Custom Part within the MIG tool and the parameters were in range with those available, your process is good.
2. You shouldn't use the xco flow with MIG. If you want to have an automated way to bring the core into an ISE project, use the create_ise.bat/.sh script file to generate a .ise project with all the required files pulled in for you.
10-18-2011 11:16 PM
10-18-2011 11:31 PM
tht worked.. :).. problem was that the bin folder in 12.1 was not added to the path.. now its working,
But again, when i run the create_ise.bat, i get an error " ../rtl/.inotes" cant be found - while executing "xfile add ../rtl/.inotes" < file "set_ise_prop.tcl"
shall i just delete that particular line from "set_ise_prop_tcl" and re-run it?...
10-18-2011 11:43 PM
ok.. i deleted those lines from "set_ise_prop.tcl" and ran it.
It generated "test.xise"
I opened it using ISE 12.1, and found that, the toplevel code needs clock inputs (as mentioned in the first post) called "c5_sys_clk" and "c4_sys_clk" (am using DDR2_SDRAMs in banks 4 and 5).
Now, what is the frequency of clock i need to provide to these inputs?
when i checked the code, these clocks are going to PLL inputs.
for eg., c5_sys_clk is going to one PLL, and tht PLL's output "CLKOUT0" goes to the MCB global input buffer and becomes "sysclk_2x"
here is the parameters defined for PLL as per the code "memc5_infrastructure.v"
parameter C_CLKOUT1_DIVIDE = 1
parameter C_CLKFBOUT_MULT = 2
parameter C_DIVCLK_DIVIDE = 1
10-19-2011 09:38 AM
Take a look at the Modifying The Clock Setup section in UG388 - http://www.xilinx.com/support/documentation/user_guides/ug388.pdf
MIG assumes the input clock frequency is the same as the memory clock frequency.
10-19-2011 10:54 PM
Thanks bethf for the reply.
Yea, I have read that portion and "Figure 3-3: Recommended System and Caliberation clock distribution" shows the clock setup.
It shows a PLL which gets external clock, gives out the 2x clocks which is then buffered by the BUFPLL_MCB and then it goes to the MIG wrapper.
Till that point everything is fine.
Now when i check in the code, I find the following files ->
1. mig_v3_4.v (the toplevel which instantiates the MIG wrapper and required infrastructure modules)
2. memc5_infrastructure.v (it has a PLL inside it, it gets the an external clock and generates the 2x clocks and buffers them through BUFPLL_MCB in the same code)
3. memc5_wrapper.v (which is the MIG wrapper and it takes the 2x clocks)
Now, whatever clock setup was there mentioned in "Figure 3-3" is present already in the file "mig_v3_4.v", just that it seems like, the PLL used ther (in memc5_infrastructure.v) just takes the input clock, and gives out 2x clock which is at same frequency.
So, that would mean, I have to use another PLL at the outside, and generate these 2x frequencies, and then provide to the module "mig_v3_4.v" ??...
( The create_ise.bat when ran, created the ise project which had the file "mig_v3_4.v" as toplevel and thats y i am using it, a part of my mind tells me that i shouldnt be using this toplevel, instead use just "memc5_wrapper.v" and then create my own clock infrastructure module with PLL and BUFPLL_MCB etc., )
please help me on this.
10-20-2011 12:00 AM